SF32LB58-MOD Hardware Design Guide¶

1. Overview¶

SF32LB58-MOD is a certified, general-purpose low-power Bluetooth MCU module built on SiFli's flagship SF32LB586VDD36 chip (Arm Cortex-M33 STAR-MC1 triple-core, up to 240MHz). It integrates a 48MHz crystal, an optional 32.768kHz crystal, and, depending on order code, in-package HPI-PSRAM, QSPI-NOR/NAND Flash, or eMMC storage into a single 24 × 24 × 3.1mm surface-mount package with 138 pins.

This guide covers module-level hardware integration: pin definitions, peripheral interfaces, electrical characteristics, power-supply requirements, reference schematics, a schematic design checklist, mechanical dimensions and PCB footprint, and product handling requirements. It is based on SiFli datasheet DS5802-SF32LB58-MOD V0.1.

For the underlying chip architecture (cores, graphics, memory subsystem, and peripherals in more depth), see SF32LB58x and the SF32LB58x Hardware Design Guide.

2. Quick Design Summary¶

2.1 Module Variants¶

2.2 Key Specifications¶

3. Functional Block Diagram¶

The module integrates the SF32LB586VDD36 chip, a 48MHz crystal, an optional 32.768kHz crystal, and, depending on SKU, in-package HPI-PSRAM, QSPI-NOR/NAND Flash, or eMMC, alongside the RF matching network and antenna feed.

4. Pin Definition¶

4.1 Pinout Diagram¶

The module exposes 138 pins around its perimeter.

4.2 Pin Definition Table¶

The module has 138 pins in total, described in the table below.

Legend: P = power; I = input; O = output; T = can be configured as high-impedance; AO = audio output; AI = audio input.

4.3 Physical Pin Description¶

The datasheet's physical pin description figure groups pins by function family — SDIO, SPI, I2C, UART, GPTIM, LCD interface (DPI/8080/SPI/JDI/DSI), GPADC, MPI, analog audio, boot mode, power supply, BT antenna, CAN/USB, and SWD/debug UART — overlaid on the SF32LB586VDD36 die outline. Use it alongside the pin definition table above when laying out signal groups on the host PCB.

5. Peripherals¶

5.1 Communication Interfaces¶

Any pin marked PAxx_I2C_UART or PBxx_I2C_UART in the table above can be configured as either I2C or UART. The chip supports up to 7 I2C interfaces and 6 UART interfaces in total.

UART — Full-duplex, up to 6Mbps baud rate, configurable data format, hardware flow control (CTS/RTS), DMA multi-packet TX/RX. UART1–3 are on HPSYS; UART4–6 are on LPSYS.

I2C — Master and Slave capable, 8-byte FIFO, DMA support, standard (100kbps), fast (400kbps), fast-mode-plus (1Mbps), and high-speed (3.4Mbps) modes, 7-bit/10-bit addressing as Master, configurable digital de-glitch filter. I2C1–4 are on HPSYS; I2C5–7 are on LPSYS.

SPI — Supports SSP/SPI (full duplex, Master or Slave) and Microwire (half duplex, Master only) formats, 4–32-bit data width, configurable clock polarity/phase, configurable chip-select polarity, 32-bit × 16-entry FIFO, DMA support. SPI1/2 are on HPSYS (max 48MHz); SPI3/4 are on LPSYS (max 24MHz).

USB2.0 HS — One high-speed Host/Device port, USB2.0-compliant, configurable endpoints, suspend/resume, session request and host negotiation protocol support, high-speed and full-speed mode support.

MPI (Memory Peripheral Interface) — Supports SPI NOR Flash (1/2/4-line, DTR mode) and SPI NAND Flash (1/2/4-line), register-mode and memory-mapped-mode access with automatic hardware switching. The module's MPI4 interface can connect external SPI NOR/NAND Flash.

SD/SDIO/eMMC — Compliant with SD 3.0 and eMMC 4.5.1; acts as Host controller with chained DMA and a 1KB FIFO. Supports SDSC/SDHC/SDXC/SDHS cards, UHS-1 (SDR12/25/50/104/DDR50), single-line/4-line/8-line SDR modes, and 4-line/8-line DDR modes.

I2S — Master-only, full-duplex, left-justified/right-justified/standard formats, 8-bit and 16-bit mono/stereo, up to 24-bit PCM width.

LCD Interface — DBI serial SPI mode (3-line/4-line, dual/quad data line) and parallel 8080 mode (8/16/24-bit bus width). Supports RGB332/RGB444/RGB565/RGB666/RGB888 color formats depending on mode. A dedicated MIPI DSI lane set (clock + 2 data lanes) is also available on pins 47–52.

5.2 Analog Signal Processing¶

12-bit GPADC — SAR ADC, 4MS/s max sample rate, 0–3.3V single-ended / ±2.1V differential input range, 8 single-ended channels (or 4 differential pairs), single/continuous measurement modes, 4 configurable time-slots per measurement, software/hardware trigger, DMA support.

Temperature Sensor — 0.2°C resolution, -40°C to 125°C range, ±3°C accuracy, polling or interrupt read-out.

Audio DAC — 2 integrated 24-bit channels, 8kHz–48kHz sample rates, differential output.

Audio PLL — Fractional-N clock generation with 48MHz/2^18 resolution, supporting 48MHz, 32.768kHz, and 44.1kHz derived sample rates.

Audio ADC — 2 integrated 24-bit channels, 8kHz–48kHz sample rates, independent per-channel gain control.

6. Electrical Characteristics¶

6.1 Absolute Maximum Ratings¶

6.2 Recommended Operating Conditions¶

6.3 DC Electrical Characteristics¶

Full tables (including input leakage, reset thresholds, and pin capacitance at both supply voltages) are provided in §5.3 of the official datasheet.

6.4 Power Consumption¶

6.5 Dual-Mode Bluetooth RF Performance¶

Supports Bluetooth 6.3, backward compatible with 5.x/4.2/4.1/4.0. Operating channel center frequency: 2402–2480MHz.

BLE transmitter (1Mbps): max power 19dBm, power control range -20 to 19dBm.

BLE receiver: sensitivity -100dBm (1Mbps), -97dBm (2Mbps), -104.5dBm (LR S2/125kbps), -107.5dBm (LR S8/500bps) @30.8% PER, dirty-off condition.

Classic BT (Basic Data Rate): max transmit power 19dBm; receiver sensitivity -96.3dBm (dirty off) / -94dBm (dirty on) @0.1% BER.

Classic BT (Enhanced Data Rate): max transmit power 13dBm; π/4-DQPSK receiver sensitivity -95.5dBm; 8DPSK receiver sensitivity -88.5dBm.

Full min/typ/max tables for all BLE 1Mbps/2Mbps/LR TX/RX performance and Classic BT BR/EDR TX/RX performance are provided in §5.5 of the official datasheet.

7. Module Power Supply¶

The module has five power interfaces: VDD_3V3, VDD_1V8, VDDIOA, VDDIOA2, and VDDIOB.

• VDD_3V3 supplies the chip's AVDD33_ANA, AVDD33_AUD, AVDD_USB rails and the module's in-package eMMC VDD (where populated). An LDO supply is recommended.
• VDD_1V8 supplies the chip's PVDD1, PVDD2, AVDD_BRF, AVDD18_DSI rails and the in-package memory.
• VDDIOA supplies the chip's VDDIOA rail, the in-package eMMC VIO (where populated), and external Flash.
• VDDIOA2 supplies the chip's VDDIOA2 rail (covering PA00–PA11).
• VDDIOB supplies the chip's VDDIOB rail.

8. Reference Schematic and Pin Assignment¶

The datasheet provides a complete reference schematic for a SF32LB58-MOD-based development board, covering power supply, reset, JTAG/SWD, UART, SDIO, LCD, MIPI DSI, and audio circuits.

The datasheet also provides a recommended pin-assignment table for that reference board, including Raspberry Pi-style header mappings for LCD_DPI_24, LCD_DSI, LCD_QSPI, and LCD_8080 display options.

Use these as the starting point for a production schematic and adapt pin selection to your product's specific peripheral mix.

9. Schematic Design Checklist¶

10. Module Dimensions and PCB Footprint¶

10.1 Module Dimensions¶

The module measures 24 × 24 × 3.1mm.

10.2 Recommended PCB Footprint¶

10.3 External Antenna Connector¶

For SKUs supporting an external antenna, the module can use a stamp-hole RF feed or an IPEX-compatible connector, depending on part number.

10.4 Module Placement in PCB Design¶

Reserve the module antenna zone so that no components, copper, traces, chassis metal, or other conductive structures overlap the RF keepout area. Use the official module datasheet and the final product enclosure as the reference for antenna clearance and validation.

• Extend the antenna area past the host board edge where possible, with the feed point close to the board edge.
• If the antenna cannot extend past the board edge, provide a generous keepout zone (no copper pour, traces, or components) and cut away host-board material beneath the antenna where possible.
• For full end-product designs, evaluate the enclosure's effect on the antenna and perform RF validation, including a final communication-range test on the finished product.

11. Product Handling¶

11.1 Storage Conditions¶

• Store products sealed in a moisture barrier bag (MBB) at <40°C / 90%RH, non-condensing.
• After opening the vacuum bag, use the module within the floor-life window specified for its moisture sensitivity level (MSL); otherwise it must be baked before a second reflow pass.

11.2 Electrostatic Discharge (ESD)¶

Follow SiFli's standard module ESD handling precautions during assembly and test.

11.3 Reflow Profile¶

The module is recommended to go through reflow only once.

11.4 Ultrasonic Vibration¶

Avoid exposing SiFli modules to vibration from ultrasonic welding or ultrasonic cleaning equipment. Ultrasonic vibration can resonate with the module's internal crystal oscillators, causing crystal failure or malfunction, and may render the module inoperable or degrade its performance.

12. Related Documents¶

• DS5802-SF32LB58-MOD Datasheet (V0.1)
• SF32LB58x Chip Introduction
• SF32LB58x Hardware Design Guide
• SF32LB58-DevKit-LCD

13. Revision History¶

This guide is based on DS5802-SF32LB58-MOD V0.1, the initial published revision. Refer to the official PDF for the authoritative and most current revision.