SF32LB52-MOD-1 Hardware Design Guide¶

1. Overview¶

SF32LB52-MOD-1 is a certified, general-purpose low-power Bluetooth MCU module built on SiFli's SF32LB525UC6 chip (Arm Cortex-M33 STAR-MC1 dual-core, up to 240MHz). It integrates a 48MHz crystal, an optional 32.768kHz crystal, and an optional in-package 64Mb OPI-PSRAM die into a single 27.9 × 18.0 × 3.1mm surface-mount package with 68 pins.

This guide covers module-level hardware integration: pin definitions, peripheral interfaces, electrical characteristics, power-supply requirements, reference schematics, a schematic design checklist, mechanical dimensions and PCB footprint, and product handling requirements. It is based on SiFli datasheet DS5203-SF32LB52-MOD-1 V0.3.

For the underlying chip architecture (cores, graphics, memory subsystem, and peripherals in more depth), see SF32LB52x and the SF32LB52x Hardware Design Guide.

2. Quick Design Summary¶

2.1 Module Variant¶

2.2 Key Specifications¶

3. Functional Block Diagram¶

The module integrates the SF32LB525UC6 chip, a 48MHz crystal, an optional 32.768kHz crystal, and — on this SKU — an in-package 64Mb OPI-PSRAM die, alongside the RF matching network and antenna feed.

4. Pin Definition¶

4.1 Pinout Diagram¶

The module exposes 68 pins around its perimeter. Pin 1 is marked at the corner near the antenna zone; pins are numbered counter-clockwise around the package.

4.2 Pin Definition Table¶

The module has 68 pins in total, described in the table below.

Legend: P = power; I = input; O = output; T = can be configured as high-impedance; AO = audio output; AI = audio input.

4.3 Physical Pin Description¶

The datasheet's physical pin description figure groups pins by function family — SDIO, SPI, I2C, UART, GPTIM, LCD interface, GPADC, MPI, analog audio, external 32K oscillator, external wake-up, and SWD/debug UART — overlaid on the SF32LB525UC6 die outline. Use it alongside the pin definition table above when laying out signal groups on the host PCB.

5. Peripherals¶

5.1 Communication Interfaces¶

Any pin marked PAxx_I2C_UART in the table above can be configured as either I2C or UART. The chip supports up to 4 I2C interfaces and 3 UART interfaces in total.

UART — Full-duplex, up to 6Mbps baud rate, configurable data format, hardware flow control (CTS/RTS), DMA multi-packet TX/RX. UART1–3 are on HPSYS; UART4–6 are on LPSYS.

I2C — Master and Slave capable, 8-byte FIFO, DMA support, standard (100kbps), fast (400kbps), fast-mode-plus (1Mbps), and high-speed (3.4Mbps) modes, 7-bit/10-bit addressing as Master, configurable digital de-glitch filter. I2C1–4 are on HPSYS; I2C5–7 are on LPSYS.

SPI — Supports SSP/SPI (full duplex, Master or Slave) and Microwire (half duplex, Master only) formats. 4–32-bit data width, configurable clock polarity/phase (SPO/SPH), configurable chip-select polarity, 32-bit × 16-entry FIFO, DMA support, up to 48MHz clock.

USB2.0 FS — One full-speed Host/Device port with configurable endpoints, suspend/resume, dynamic FIFO sizing, session request and host negotiation protocol support, and an integrated USB2.0 FS PHY.

MPI (Memory Peripheral Interface) — Supports SPI NOR Flash (1/2/4-line) and SPI NAND Flash (1/2/4-line), register-mode and memory-mapped-mode access with automatic hardware switching. The module's MPI2 interface can connect external SPI NOR/NAND Flash. If Flash is already populated inside the module, MPI2's six external signals (PA12, PA13, PA14, PA15, PA16, PA17) are unavailable externally.

SD/SDIO/eMMC — Compliant with SD 3.0, SDIO 3.0, and eMMC 4.5.1; supports SDSC/SDHC/SDXC/SDHS cards, SDR12/25/50, single-line and 4-line SDR modes, 2KB FIFO, DMA data movement, up to 48MHz (no DDR). Note: the SDIO interface shares IO with MPI2 — the two cannot be used simultaneously.

I2S — Master/Slave, full-duplex, left-justified/right-justified/standard formats, 8-bit and 16-bit mono/stereo, up to 24-bit PCM width.

LCD Interface — DBI serial SPI mode (3-line/4-line, dual/quad data line) and parallel 8080 mode (8/16/24-bit bus width). Supports RGB332/RGB444/RGB565/RGB666/RGB888 color formats depending on mode.

5.2 Analog Signal Processing¶

12-bit GPADC — SAR ADC, 4MS/s max sample rate, 0–3.3V single-ended / ±2.1V differential input range, 7 single-ended channels + 1 battery-voltage channel (or 3 differential pairs), single/continuous measurement modes, 4 configurable time-slots per measurement, software/hardware trigger, DMA support.

Temperature Sensor — 0.2°C resolution, -40°C to 125°C range, ±3°C accuracy, polling or interrupt read-out.

Audio DAC — One 24-bit DAC output path, 8kHz–48kHz sample rates, differential output.

Audio PLL — Fractional-N clock generation with 48MHz/2^18 resolution, supporting 48MHz, 32.768kHz, and 44.1kHz derived sample rates.

Audio ADC — One 24-bit Sigma-Delta ADC input path, 8kHz–48kHz sample rates.

6. Electrical Characteristics¶

6.1 Absolute Maximum Ratings¶

Exceeding the values in the table below may permanently damage the module. These are stress ratings only; functional operation beyond the recommended operating conditions in §6.2 is not implied. Prolonged exposure to absolute-maximum conditions may reduce module reliability.

6.2 Recommended Operating Conditions¶

6.3 DC Electrical Characteristics (3.3V, 25°C)¶

VDD is the I/O supply rail; VOH/VOL are measured under high-impedance load.

6.4 Power Consumption¶

6.5 Dual-Mode Bluetooth RF Performance¶

Supports Bluetooth 6.3, backward compatible with 5.x/4.2/4.1/4.0. Operating channel center frequency: 2402–2480MHz.

BLE transmitter (1Mbps): max power 19dBm, power control range -20 to 19dBm, max/min modulation index 250kHz/210kHz typ, initial carrier frequency tolerance ±20kHz typ.

BLE receiver (1Mbps): sensitivity -100dBm (dirty off) / -99.3dBm (dirty on) @30.8% PER, co-channel C/I 7dB.

Classic BT (Basic Data Rate): max transmit power 18dBm; receiver sensitivity -96.3dBm (dirty off) / -94dBm (dirty on) @0.1% BER.

Classic BT (Enhanced Data Rate): max transmit power 13dBm; π/4-DQPSK receiver sensitivity -95.5dBm; 8DPSK receiver sensitivity -88.5dBm.

Full min/typ/max tables for all BLE 1Mbps/2Mbps TX/RX performance and Classic BT BR/EDR TX/RX performance are provided in §5.5 of the official datasheet.

7. Module Power Supply¶

The module has a single main power input, VSYS, which can be supplied directly from a Li-ion/Li-Po battery (3.2–4.7V) or from a DCDC/LDO regulator (3.7–4.7V, 3.8V recommended).

VBATS is the battery-voltage sense pin, sampled internally by an ADC over a 0–4.7V range. Do not use an external resistor divider on VBATS — connect the signal to be measured directly to the pin.

VDD33_VOUT2 is the output of the module's internal 3.3V LDO and can supply up to 150mA to external peripherals; the total capacitance on this rail must not exceed 7.4µF.

8. Reference Schematic and Pin Assignment¶

The datasheet provides a complete reference schematic for a SF32LB52-MOD-1-based development board, covering power supply, reset, JTAG/SWD, UART, SDIO, LCD, and audio circuits.

The datasheet also provides a recommended pin-assignment table for that reference board.

Use these as the starting point for a production schematic and adapt pin selection to your product's specific peripheral mix.

9. Schematic Design Checklist¶

10. Module Dimensions and PCB Footprint¶

10.1 Module Dimensions¶

The module measures 27.9 × 18.0 × 3.1mm.

10.2 Recommended PCB Footprint¶

10.3 External Antenna Connector¶

For SKUs supporting an external antenna, the module uses a first-generation connector footprint compatible with:

• Hirose U.FL series
• I-PEX MHFI connectors
• Amphenol AMC connectors

10.4 Module Placement in PCB Design¶

If the end product uses an on-board module design, reserve space so that no other components or metal areas overlap the module's PCB antenna zone, to avoid degrading radiation efficiency. Plan the module's position on the host board to minimize impact on antenna performance.

Recommended practice:

• Extend the module's antenna area past the host board edge, with the feed point close to the board edge.

• If the antenna cannot extend past the board edge, provide a keepout zone of at least 15mm around the PCB antenna — no copper pour, traces, or components — and cut away the host board material beneath the antenna where possible.

• Keep the antenna feed point close to the board edge even in the keepout-zone layout.
• For full end-product designs, evaluate the enclosure's effect on the antenna and perform RF validation, including a final communication-range test on the finished product.

11. Product Handling¶

11.1 Storage Conditions¶

• Store products sealed in a moisture barrier bag (MBB) at <40°C / 90%RH, non-condensing.
• Module moisture sensitivity level (MSL): 3.
• After opening the vacuum bag, use the module within 168 hours at 25±5°C / 60%RH; otherwise it must be baked before a second reflow pass.

11.2 Electrostatic Discharge (ESD)¶

• Human Body Model (HBM): ±2000V
• Charged Device Model (CDM): ±500V

11.3 Reflow Profile¶

The module is recommended to go through reflow only once.

11.4 Ultrasonic Vibration¶

Avoid exposing SiFli modules to vibration from ultrasonic welding or ultrasonic cleaning equipment. Ultrasonic vibration can resonate with the module's internal crystal oscillators, causing crystal failure or malfunction, and may render the module inoperable or degrade its performance.

12. Related Documents¶

• DS5203-SF32LB52-MOD-1 Datasheet (V0.3)
• SF32LB52x Chip Introduction
• SF32LB52x Hardware Design Guide
• SF32LB52-DevKit-LCD

13. Revision History¶

This guide is based on the datasheet content above; refer to the official PDF for the authoritative and most current revision.