SF32LB58x Hardware Design Guide¶

1. Introduction¶

This hardware design guide provides recommendations and reference material for products based on the SF32LB58x family of high-performance AIoT microcontrollers. It is intended for hardware engineers, PCB designers, and product developers building battery-powered products with rich user interfaces, large memory, dual-mode Bluetooth, audio, high GPIO count, and low-power standby requirements.

The guide covers the complete hardware development process, including PMIC and power distribution, BGA256 fanout, HDI stack-up planning, clock circuits, RF design, MIPI-DSI, USB2.0 High-Speed, SDIO/eMMC, audio circuits, PCB layout, validation, and manufacturing preparation. Following these guidelines helps reduce risk in dense BGA/HDI designs, protect signal integrity on high-speed interfaces, and keep the product aligned with the SF32LB58x power, package, and production requirements.

This document assumes a basic understanding of embedded hardware design, schematic capture, and high-density PCB layout. It complements the SF32LB58x datasheet, user manual, official hardware application note, reference design package, and SiFli Approved Vendor List, which remain the authority for electrical specifications, pin multiplexing, package dimensions, component qualification, and production limits.

2. Development Resources¶

3. Device Overview¶

3.1. Architecture¶

3.2. Variants¶

Specific SF32LB58x ordering codes and co-packaged memory combinations should be confirmed from the latest datasheet and AVL before schematic freeze. From a board-design perspective, treat the whole SF32LB58x family as a BGA256, HDI-only platform with model-dependent SIP memory and external storage options through MPI4, SD1, and SD2.

3.3. Packages¶

3.4. Major Hardware Features¶

• BGA256 package with 0.4 mm pitch and dense power/GPIO fanout.
• HDI PCB process required; the design is not PTH-compatible.
• Integrated PMU with 2 BUCK outputs and 3 internal LDO outputs.
• Optional system PMIC SF30147C for watch-class system power distribution.
• MIPI-DSI, USB2.0 HS, SDIO/eMMC, RF, audio, and dense BGA fanout require early stack-up and impedance confirmation.

3.5. Typical Applications¶

SF32LB58x is recommended for premium connected products that need advanced graphics, large memory, high GPIO count, multimedia, and edge AI capability, including:

• Premium smartwatches, sports watches, and outdoor wearables
• Advanced cycling computers and vehicle-mounted dashboards
• Smart displays and connected dashboards
• AI-enabled wearable devices
• Edge AI and sensor-fusion systems
• High-resolution LVGL-based HMI devices
• Portable medical and industrial terminals
• Bluetooth + Wi-Fi accessories that use an external SDIO Wi-Fi device

4. Design at a Glance¶

4.1. Hardware Architecture¶

4.2. Hardware Design Flow¶

4.3. How to Use This Guide¶

Use this guide in board-review order: confirm the package and SIP-memory configuration, lock the HDI stack-up and PMIC strategy, review boot storage and display routing, then verify clocks, RF, USB, audio, debug, and production test access. Section 5 is the schematic baseline, Section 6 is the PCB implementation baseline, and Section 7 is the release checklist.

4.4. Review Evidence Pack¶

Before prototype release, archive the schematic PDF, PCB stack-up, via/process capability statement, impedance report, DRC report, AVL cross-check, and focused layout screenshots for the PMIC, BUCK inductors, DSI, USB, SDIO/eMMC, RF, crystals, audio, BGA fanout, ground return, and ESD entry points.

5. Schematic Design Guidelines¶

This chapter groups the SF32LB58x schematic topics by engineering function: power, clock generation, RF, user interfaces, storage and connectivity, and manufacturing support. Each subsection starts from the design intent, then captures the circuit requirements, common risks, and release checks for the SF32LB58x platform.

5.1. Power System¶

5.1.1. Power Supply¶

The SF32LB58x series has a built-in PMU power unit supporting 2 BUCK outputs, which require an external inductor and capacitor returning to the internal power input, plus 3 internal LDO outputs that require external capacitors. For watch-class designs, the SF32LB58x can be paired with SiFli's PMIC chip SF30147C, which supplies power to both the SF32LB58x and its associated peripherals.

5.1.1.1. SiFli PMIC Power Distribution¶

The SF30147C is a highly integrated, high-efficiency power management chip for ultra-low-power wearable products. It integrates 4 LDOs, each with a wide input/output voltage range and up to 100 mA load current. For different peripherals, the SF30147C integrates 7 low-leakage, low-Ron load switches: 2 high-voltage switches for peripherals driven directly from battery voltage (such as an audio PA), and 5 low-voltage switches for 1.8 V-powered peripherals. The SF32LB58x uses two GPIOs to emulate a TWI signal to control the SF30147C.

Refer to the SF30147C chip datasheet for full details.

5.1.1.2. SF32LB58x Power Requirements¶

The SF32LB58x series integrates the following PMU power specifications.

Other power pins requiring external supply are specified below.

5.1.1.3. Recommended Capacitor Values¶

5.1.1.4. BUCK Inductor Selection¶

5.1.1.5. Power-Up Sequencing and Reset¶

The SF32LB58x series has built-in POR (Power-On Reset) and BOR (Brownout Reset), and also supports an external hardware reset signal, RSTN.

The RSTN reset signal should be pulled up to the PVDD1 input voltage domain, with a 0.1 uF capacitor to ground forming an RC delayed reset.

5.1.1.6. Typical Power Circuit¶

The SF32LB58x series can use SiFli's PMIC SF30147C to supply its power rails; see Table 5-1 for the assignment. The chip package also has 2 built-in BUCK outputs and 3 built-in LDO outputs.

5.1.1.7. Power Design Checklist¶

• Confirm the selected model's PVDD1/PVDD2 supply range (1.71 V–3.6 V) matches the actual power scheme
• BUCK inductor meets 4.7 uH, DCR ≤ 0.4 Ω, Isat ≥ 500 mA
• PVDD1/PVDD2, BUCK1/2_LX/FB, LDO_VOUT1, VDD_RET, and VDD_RTC decoupling capacitors use the recommended values listed in this section
• If using SF30147C, the voltage/current allocation of the 7 load switches matches peripheral requirements
• The RSTN reset circuit's RC delay meets the device's reset timing requirements

5.1.2. Operating Modes and Wake Sources¶

The low-power strategy should be reviewed together with PBR functions, wake-capable interrupts, storage power switches, sensor supplies, and external PMIC load switches.

The SF32LB58x series provides 6 PBR interfaces, with these key characteristics:

1. PBR0 transitions from 0 to 1 during power-up, useful for driving certain external LSWs; PBR1-PBR5 default to output 0;
2. PBR0-PBR5 can all act as outputs in both Standby and Hibernate modes;
3. PBR0-PBR5 can output the LPTIM signal;
4. PBR0-PBR5 can output a 32 kHz clock signal;
5. PBR0-PBR3 can be configured as inputs for wake-up signal input — the MCU does not receive an interrupt while it is awake.

All GPIOs on the SF32LB58x series support wake-up in light/deep sleep mode. In Standby and Hibernate modes, 16 wake-capable interrupt sources are supported — 6 on PA and 10 on PB.

5.2. Clock Generation¶

The SF32LB58x series requires 2 external clock sources: a 48 MHz main crystal and a 32.768 kHz RTC crystal.

See the SiFli Approved Vendor List for detailed qualified-material information.

5.3. RF¶

The SF32LB58x's RF front end uses on-chip integrated wideband matching-filter technology, so only a 50 Ω controlled-impedance RF PCB trace is required. A π-matching network for spurious filtering and antenna matching should be reserved in the design.

5.4. User Interfaces¶

5.4.1. Display¶

5.4.1.1. MIPI DSI Display Interface¶

The SF32LB58x series supports a 2-lane MIPI DSI display interface.

5.4.1.2. SPI/QSPI Display Interface¶

The SF32LB58x series supports 3/4-wire SPI and Quad-SPI interfaces for connecting an LCD panel — the big core uses LCDC1 on PA, the little core uses LCDC2 on PB.

5.4.1.3. MCU8080 Display Interface¶

The SF32LB58x series supports an MCU8080 interface for connecting an LCD panel.

5.4.1.4. DPI Display Interface¶

The SF32LB58x series supports a DPI interface for connecting an LCD panel.

5.4.1.5. JDI Display Interface¶

The SF32LB58x series supports both parallel and serial JDI interfaces for connecting an LCD panel, multiplexed onto either LCDC1 (PA) or LCDC2 (PB) signals — LCDC2 (PB) is recommended.

5.4.2. Touch and Backlight¶

The SF32LB58x series supports an I2C-format touch controller interface with a touch-status interrupt input, plus 1 PWM signal to control backlight-driver enable and brightness.

5.4.3. Audio¶

The SF32LB58x series provides a variety of audio-related interfaces, with the following characteristics:

1. Supports 3 groups of I2S; I2S1 is input-only, while I2S2 and I2S3 support both input and output. All 3 I2S groups only support Master mode, not Slave mode;
2. I2S1 is recommended for an I2S MIC input;
3. I2S2 is recommended for an audio DAC;
4. I2S3 is recommended for an audio codec;
5. Supports 2 PDM MIC inputs;
6. Supports 2 analog MIC inputs, each requiring a DC-blocking capacitor of at least 2.2 uF; analog MIC power is supplied from the SF32LB58x's MIC_BIAS;
7. Supports an external analog audio PA — both DAC output traces should be routed as differential pairs with 3D shielding, and additionally satisfy: trace parasitic capacitance < 10 pF, trace length < 2 cm;
8. Supports stereo analog headphone connection.

The SF32LB58x's analog MIC input supports both single-ended and differential modes, with a series 2.2 uF capacitor in either case; AU_ADC1P/AU_ADC1N/AU_ADC2P/AU_ADC2N connect to the SF32LB58x side. On the analog output side, AU_DAC1P/AU_DAC1N/AU_DAC2P/AU_DAC2N are SF32LB58x outputs that can drive either a stereo headphone PA input or an external analog audio PA input. Both the analog audio PA and the I2S audio PA are configured over I2C3.

5.4.4. Buttons¶

5.4.4.1. Power and Long-Press-Reset Button¶

PB54 is the recommended power-key signal for the SF32LB58x series, combining a short-press power on/off function and a long-press reset function on a single button. The design is active-high; holding the button for more than 10 seconds triggers an automatic chip reset.

5.4.4.2. Function Button or Rotary Encoder¶

The SF32LB58x series supports function-button input and rotary-encoder signal input, both of which need to be pulled up. It also supports a light-tracking sensor, recommended over the I2C4 interface.

5.4.5. Vibration Motor¶

The SF32LB58x series supports multiple PWM outputs, which can drive a vibration motor.

5.5. Storage and Connectivity¶

5.5.1. Boot Configuration¶

The SF32LB58x series provides a Mode pin to configure the boot mode.

5.5.2. Storage¶

The SF32LB58x series supports MPI3 or MPI4 interfaces for external NOR Flash and SPI NAND Flash, and an SD1 interface for external SD NAND and eMMC.

5.5.2.1. QSPI NAND Flash Interface¶

The SF32LB58x EVB reference board uses MPI4 by default to connect an external SPI NAND Flash device.

5.5.2.2. SDIO eMMC/Micro SD Interface¶

The SF32LB58x series supports 2 SDIO interfaces. On the EVB, SD1 connects to eMMC or SD NAND by default, and SD2 connects to an SD card or Wi-Fi chip.

SD1 uses 12 GPIOs (PA00-PA11) powered from the VDDIOA2 domain, supporting 1.8 V or 3.3 V, selectable according to the peripheral's interface level. SPI NAND Flash and eMMC are recommended at 1.8 V; SD NAND Flash dies only support 3.3 V interface levels, so VDDIOA2 must be set to 3.3 V in that case.

5.5.3. USB¶

The SF32LB58x series USB supports USB2.0 HS in both Host and Device modes. A TVS diode must be connected across USB DP and DM to ground, with junction capacitance below 5 pF; DP/DM PCB traces should be controlled to 90 Ω differential impedance.

5.6. Manufacturing¶

5.6.1. Debug and Download Interface¶

The SF32LB58x series supports the Arm®-standard SWD debug interface for connection to EDA tools for single-step debugging. When connecting a SEGGER® J-Link® probe, its power source must be reconfigured for external supply, powered from the SF32LB58x board itself.

The SF32LB58x offers 1 SWD interface plus 6 selectable UART interfaces for debug output.

5.6.2. Production Flashing and Hardware Access¶

Production flashing, recovery, and calibration access should be planned before enclosure and fixture freeze. At minimum, preserve access to power, ground, SWD, required UART debug outputs, boot/configuration pins, and any board-level reset or PMIC control points needed to recover a non-booting image.

5.6.3. Schematic and PCB Drawing Checklists¶

• The power scheme (integrated PMU direct supply, or paired with SF30147C) matches the system power budget
• The Mode boot-configuration pin has an external 10 kΩ resistor and a reserved test point on production boards
• The 48 MHz/32.768 kHz crystal specifications match the recommendations, with layer-2 GND removed beneath the crystal
• Storage interface selection (MPI4/SD1/SD2) matches the boot configuration, and the PA43 external Flash power-control pin is confirmed
• Display interface selection (MIPI-DSI/SPI-QSPI/MCU8080/DPI/JDI) matches the LCDC1/LCDC2 pin assignment
• Debug port (SWD + 6x UART) pins are assigned as needed, with UART RXD internal pull-up enabled
• Audio interface I2S/PDM and analog-audio multiplexing has been verified, with differential-trace budget satisfied
• USB DP/DM has a parallel TVS with junction capacitance < 5 pF

6. PCB Layout Guidelines¶

6.1. Package Footprint Design¶

The SF32LB58x series uses a BGA256 package, 8.5 mm x 6.5 mm x 0.94 mm, 0.4 mm pitch. Refer to the official Datasheet for full package qualification data.

6.2. PCB Stack-Up¶

The SF32LB58x series layout supports single- or double-sided assembly. The PCB must be an HDI board — PTH is not supported; a 6HDI-2 stack-up is recommended.

6.3. General PCB Design Rules¶

Refer to the general PCB design-rule figure in the official Datasheet (dimensions in mm).

6.3.1. Blind Via Design¶

Refer to the blind-via design figures (layers 1-2 and 1-3) in the official Datasheet (dimensions in mm).

6.3.2. Buried Via Design¶

Refer to the buried-via design figure (layers 2-5) in the official Datasheet (dimensions in mm).

6.4. Trace Fanout¶

The first two rows of BGA balls are fanned out on the top layer; the remaining balls are fanned out through vias to inner layers.

6.5. Clock Interface Routing¶

Place the crystal inside a shield can, more than 1 mm from the PCB board edge, and as far as possible from heat-generating components (such as PA, charging, and PMU circuitry) — ideally more than 5 mm away — to avoid affecting crystal frequency offset. Keep the crystal keep-out zone at least 0.25 mm from other metal or components.

Route the 48 MHz crystal on the top layer with a length of 3-10 mm, trace width 0.075 mm, with full 3D shielding, and route away from VBAT, DC/DC, and high-speed signal lines. Keep the top layer and adjacent layer beneath the 48 MHz crystal area clear of any other routing.

Route the 32.768 kHz crystal on the top layer with a length ≤10 mm, trace width 0.075 mm, and 32K_XI/32K_XO parallel-trace spacing ≥0.15 mm, with full 3D shielding. Keep the top layer and adjacent layer beneath the crystal area clear of any other routing.

6.6. RF Interface Routing¶

Place the RF matching circuit as close to the chip as possible, not near the antenna end. Place the AVDD_BRF RF power decoupling capacitor as close to the chip pin as possible, with its ground pin vias landing directly on the main ground plane.

Route RF traces on the top layer where possible to avoid vias that would degrade RF performance; use a trace width greater than 10 mil, apply full 3D shielding, and avoid sharp or right angles. Add extra shielding ground vias along both sides of the RF trace, and control the RF trace to 50 Ω impedance. Keep DC-DC, VBAT, and high-speed digital signals (such as the crystal, high-frequency clocks, and I2C/SPI/SDIO/I2S/UART interface signals) out of the RF routing area. AVSS_RRF, AVSS_TRF, AVSS_TRF2, AVSS_VCO, and AVSS_BB are RF circuit ground pins that must be well grounded — place blind vias directly on their pads connecting to the main ground.

6.7. Audio Interface Routing¶

Place the AVDD33_AUD audio-supply decoupling capacitor close to its pin, with its ground pin well connected to the main ground. Place the MIC_BIAS microphone-supply decoupling capacitor close to its pin, similarly well grounded. Place the AUD_VREF decoupling capacitor close to its pin.

AU_ADC1P/AU_ADC1N and AU_ADC2P/AU_ADC2N are the two analog input pairs — place associated components as close to their pins as possible, route each P/N pair as a differential line with as short a trace length as possible, apply 3D shielding to the differential pair, and keep other strongly interfering signals away from these traces.

AU_DAC1P/AU_DAC1N and AU_DAC2P/AU_DAC2N are the two analog output pairs — place associated components as close to their pins as possible, route each P/N pair as a differential line as short as possible and under 2 mm, with trace parasitic capacitance below 10 pF and a differential trace width of 0.075 mm. Apply 3D shielding to the differential pair, and keep other strongly interfering signals away from these traces.

6.8. USB Interface Routing¶

Place the AVDD33_USB decoupling capacitor close to its pin, and place the USB2_REXT calibration resistor close to its pin. USB traces must pass through the ESD-protection component pins before reaching the chip, with the ESD device's ground pin well connected to the main ground. Route USB DP/DN as a differential pair controlled to 90 Ω differential impedance, with 3D shielding applied.

6.9. SDIO Interface Routing¶

The SF32LB58x provides 2 SDIO interfaces, SDIO1 and SDIO2. Route all signals of each SDIO interface together rather than splitting them — total trace length ≤50 mm, with intra-group length control ≤6 mm. Apply 3D shielding to the SDIO clock signal, and shield the DATA and CMD signals as well.

6.10. DSI Interface Routing¶

Place the AVDD18_DSI decoupling capacitor close to its pin, and place the DSI_REXT calibration resistor close to its pin. Route DSI signals as differential pairs controlled to 100 Ω differential impedance, with clock and data length-matched: intra-pair skew ≤0.5 mm and inter-pair skew ≤2 mm. Apply 3D shielding to each differential pair.

6.11. DC-DC Circuit Routing¶

Place the DC-DC power inductor and decoupling capacitors close to the chip pins. Keep BUCK_LX traces as short and wide as possible to minimize loop inductance in the DC-DC circuit. Add extra ground vias on all DC-DC output decoupling-capacitor ground pins connecting to the main ground plane. The BUCK_FB feedback trace must not be too thin — keep it above 0.25 mm. Prohibit copper pour on the top layer beneath the power inductor, keep the adjacent layer as a complete reference ground, and avoid routing other traces through the inductor area.

6.12. Power Supply Routing¶

PVDD1 and PVDD2 are the power inputs to the built-in PMU module — place their decoupling capacitors close to the pins and keep the traces as wide as possible, never below 0.5 mm. PVSS1 and PVSS2 are PMU module ground pins that must be connected to the main ground through vias — avoid leaving them floating, which would affect overall PMU performance.

6.13. LDO and IO Power Input Routing¶

Place decoupling capacitors for all LDO outputs and IO power inputs close to their respective pins, with trace widths meeting the input current requirement — keep traces as short and wide as possible to reduce power-rail ripple and improve system stability.

6.14. Other Interface Routing¶

GPADC pin signal nets require full 3D shielding and must be kept away from other interference sources, such as battery-level sensing and temperature-sensing circuits.

Clock input/output pin signal nets, such as the 32 kHz output, likewise require full 3D shielding and must be kept away from other interference sources.

6.15. Chip Ground Routing¶

The ground network under the SF32LB58x chip's central area must be fully connected by traces, ensuring an adequate ground plane connected to the main ground plane through blind/buried vias.

6.16. EMI & ESD¶

Avoid long top-layer traces outside the shield can, especially for clock and power interference sources — route them on inner layers where possible. Place ESD protection devices close to the connector pins, routing signals through the ESD device before anything else to avoid signal branching. Ensure ESD device ground pins connect to the main ground through vias, with short and wide ground pad traces to reduce impedance and improve ESD performance.

6.17. Other Considerations¶

Place USB charging-line test points before the TVS diode, and place the battery-holder TVS diode before the platform connection — route so the signal always passes through the TVS before reaching the chip. Keep TVS ground-pin traces as short as possible.

To keep solder mask off the pads and preserve solder-joint reliability, vias in BGA pads must land at the center of the ball — avoid off-center placement. For improved manufacturability yield, refer to the BGA ball-connection reference figures.

7. Design Review Checklist¶

• Confirmed the co-packaged Flash/PSRAM combination of the selected model matches the product requirement
• PMU supply (PVDD1/PVDD2/BUCK/LDO) and all other power pins are within the Datasheet voltage ranges
• BUCK inductor meets 4.7 uH ± tolerance, DCR ≤ 0.4 Ω, Isat ≥ 500 mA
• 48 MHz and 32.768 kHz crystals meet the recommended specifications, with routing and keep-out zones satisfied
• RF trace is 50 Ω impedance, with the matching network placed close to the chip
• Storage boot configuration (MPI4/SD1/SD2) matches the Mode boot pin setting
• Display interface (MIPI-DSI/SPI-QSPI/MCU8080/DPI/JDI) trace impedance and length-matching requirements are satisfied (DSI 100 Ω differential, SDIO intra-group ≤6 mm)
• USB and SDIO differential trace impedance and length matching meet requirements
• SWD/6x UART debug pins and production test points are reserved
• BGA pad vias are centered, and the ground plane beneath the chip is fully connected
• Key component part numbers have been verified against the latest SiFli Approved Vendor List
• The review evidence pack includes stack-up/process capability, impedance, DRC, AVL, and focused layout screenshots
• Open schematic, layout, and manufacturing questions are closed or explicitly tracked before prototype release

8. Related Documents and References¶

Use the latest official documents when checking electrical limits, package data, pin multiplexing, software configuration, and component qualification.

9. Appendices¶

The appendices collect application and reference-design context. Use them as review aids after the main schematic and PCB rules in Sections 5 and 6 have been applied.

Appendix A. A Typical Smart Wearable or Smart Terminal¶

A typical SF32LB58x wearable or smart-terminal design includes the MCU, PMIC, high-resolution display, touch controller, boot storage, external memory or eMMC, sensors, vibration motor, audio input/output, Bluetooth antenna, crystals, USB, debug access, and production test access. The BGA256 package and high-speed display/storage interfaces make HDI process selection part of the system architecture, not just a PCB-layout detail.

10. Revision History¶