SF32LB56-MOD Hardware Design Guide¶

1. Introduction¶

SF32LB56-MOD is SiFli's general-purpose low-power Bluetooth MCU module family, built on the SF32LB56xV series.

This guide presents DS5602-SF32LB56-MOD Technical Specification V0.3 as an integration-focused hardware reference for schematic design, layout planning, validation, and production release. It preserves the module-specific details from DS5602, including memory variants, the 89-pin interface, three power rails, display/audio/storage interfaces, antenna placement rules, handling requirements, and the schematic checklist.

2. Device Overview¶

2.1 Architecture¶

SF32LB56-MOD uses an SF32LB56xV-series dual-core MCU platform with an HCPU for application and graphics workloads and an LCPU for low-power always-on tasks. The HCPU is an Arm Cortex-M33 STAR-MC1 core running up to 240MHz; the LCPU is an Arm Cortex-M33 STAR-MC1 core running up to 96MHz. Both cores support FPU and MPU functions.

The module also provides Bluetooth 6.3 wireless connectivity, display acceleration, audio input/output, external-memory interfaces, USB2.0 FS, SD/SDIO/eMMC, I2S, UART, I2C, SPI, PWM, GPADC, and debug/download access.

2.2 Variants¶

2.3 Major Hardware Features¶

2.4 Typical Applications¶

Typical applications include high-end smart watches, smart bands, wearable medical equipment, fitness equipment, e-bike control panels, car keys, wearable vehicle remote controls, smart appliances, smart locks, graphical HMI devices, industrial sensor centers, industrial monitoring terminals, low-power sensor hubs, and Bluetooth mesh devices.

3. Design at a Glance¶

3.1 One-Page Engineering Summary¶

3.2 Recommended External Components¶

3.3 Power Tree¶

VDD_3V3 powers the MCU PVDD, AVDD33_ANA, AVDD33_AUD, AVDD_BRF, VDDIOA2, and module internal Flash. SiFli recommends using an LDO for this rail. VDD_1V8 powers the MCU co-packaged memory. VDDIO powers the MCU VDDIOA/VDDIOB I/O ports.

3.4 System Block Diagram¶

The module block diagram shows the SF32LB56xV MCU, memory resources, RF path, antenna option, power inputs, and external interface groups.

4. Hardware Design Flow¶

4.1 Design Sequence¶

1. Select the memory variant based on firmware size, graphics assets, external storage needs, and cost target.
2. Choose PCB antenna or external antenna variant before mechanical freeze.
3. Define the power architecture for VDD_3V3, VDD_1V8, and VDDIO, and confirm simultaneous power-up.
4. Assign display, storage, USB, audio, sensor, wake, debug, and production-test pins.
5. Resolve shared-resource conflicts, especially SDIO versus MPI3 and the internally used PA06–PA11 Flash pins.
6. Add decoupling, ESD, PWRKEY pulldown, LCD series resistors, and debug UART series resistors.
7. Place the module with the required antenna clearance and keep-out.
8. Review the schematic and PCB against the checklist in Section 7 before release.

4.2 Review Sequence¶

Use a staged review sequence: schematic review, pin-mux review, power-up review, RF/antenna review, layout review, first-article bring-up review, RF validation, environmental/reliability review, and production-test review.

4.3 Milestones¶

5. Schematic Design¶

5.1 Power System¶

5.1.1 Power Supply¶

VDD_3V3, VDD_1V8, and VDDIO must power up at the same time. Place a 4.7uF capacitor close to each module power pin. Although VDDIO can operate from 1.7V to 3.6V, the datasheet separately notes that PA00–PA11 are fixed at 3.3V and do not follow VDDIO.

5.1.2 Operating Modes¶

BOOT_MODE selects boot behavior: high for download mode and low for user mode. Keep the BOOT_MODE network deterministic during reset and production programming. PB32/PWRKEY supports active-high 10s long-press reset and requires a 10k pulldown.

5.2 Timing and RF¶

5.2.1 Clock¶

The module platform uses a 48MHz crystal oscillator and supports low-power RC oscillators at 1MHz/48MHz, an ultra-low-power 10kHz RC oscillator, and an optional 32.768kHz crystal oscillator. Keep clock-related layout and grounding consistent with the module reference design and avoid ultrasonic processes that can mechanically stress the internal crystal.

5.2.2 RF¶

The module supports PCB on-board antenna or an external antenna through an IPEX-compatible connector. Validate communication distance and RF performance in the final enclosure, not only on an open bench.

5.3 User Interfaces¶

5.3.1 Display¶

The LCD controller supports DBI serial SPI mode, Dual-SPI, Quad-SPI, 8080 parallel mode, DPI/RGB, and JDI. The recommended pin-assignment figure in the datasheet maps LCD_DPI_24, LCD_DPI_8, LCD_QSPI, LCD_8080, E-Paper, and Raspberry Pi-style groups to module pins.

Add 33–100 ohm series resistors on LCD RGB signal lines. Keep RGB, SPI display, and touch-panel routing short and consistent, and reserve ESD protection on exposed touch or connector interfaces.

5.3.2 Audio¶

The module exposes analog audio DAC outputs, MIC_BIAS, MIC_ADC_IN, I2S, and PDM-capable pins. The audio DAC is a 24-bit output path supporting 8kHz to 48kHz sample rates with 109dB SNR and dynamic range. The audio ADC is a 24-bit Sigma-Delta input path supporting 8kHz to 48kHz sample rates with 99dB SNR and dynamic range.

Route analog audio away from noisy switching nodes, LCD clocks, and antenna feed structures. Keep MIC_BIAS and MIC_ADC_IN filtering close to the attached microphone circuit.

5.3.3 Buttons¶

PB32 is the PWRKEY input and supports active-high 10s long-press reset. Add the required 10k pulldown and ensure the button circuit cannot float during shipping, deep sleep, or power sequencing.

5.3.4 Motor and PWM Loads¶

Pins marked GPTIM in the datasheet's recommended pin-assignment figure support PWM output. Use external drivers for motors, backlights, buzzers, or other loads; do not drive inductive or high-current loads directly from module GPIO.

5.4 Storage and Connectivity¶

5.4.1 Storage¶

The module family provides SKU-dependent main Flash, 4+8MB OPI-PSRAM, and 1MB backup QSPI-NOR Flash. MPI3 can connect SPI NOR or SPI NAND externally, but PA06–PA11 are connected to module internal Flash by default and are unavailable externally. SDIO and MPI3 share I/O resources and cannot be used at the same time.

5.4.2 Sensors¶

GPADC supports 12-bit conversion, up to 4MS/s sample rate, 0–3.3V single-ended input range, -2.1V to +2.1V differential input range, software/hardware trigger, and DMA. Pins marked GPADC_CHx support analog input; keep analog routes short, filtered, and away from LCD and RF switching noise.

5.4.3 UART/I2C¶

UART supports full-duplex operation up to 6Mbps. I2C supports standard 100kbps, fast 400kbps, fast-mode plus 1Mbps, and high-speed 3.4Mbps modes. Many GPIOs are multiplexed as PAxx_I2C_UART or PBxx_I2C_UART; confirm the final mux plan before schematic freeze.

UART4_TXD on pin 6 and UART4_RXD on pin 7 are the default print serial port and support program download/debug. PA16 and PA17 can be multiplexed as DBG_UART and require 100 ohm series resistors when used for program download/debug.

5.4.4 USB, SPI, SDIO, and I2S¶

USB2.0 FS supports Host/Device mode with integrated PHY. SPI supports SSP/SPI and Microwire formats; HPSYS SPI reaches up to 48MHz and LPSYS SPI up to 24MHz. SDMMC1 supports SD 3.0, SDIO 3.0, and eMMC 4.5.1 with SDR and DDR modes; SDMMC2 supports SD/SDIO/eMMC functions with SDR modes up to 48MHz. I2S supports master/slave, full duplex, left/right/standard formats, and up to 24-bit PCM width.

5.5 Manufacturing¶

5.5.1 Debug¶

SWDIO on pin 79 and SWCLK on pin 80 are SWD debug/download pins. Keep SWD accessible on early prototypes and production fixtures. Also expose the default UART4 download/debug path unless the product has another approved programming path.

5.5.2 Production¶

Reserve production access for power, ground, boot mode, reset/PWRKEY, SWD, UART download, and any board-level calibration or RF test interface. Final test software should cover boot, Flash, display, touch, audio, USB, sensors, RF communication, sleep/wake behavior, and current consumption.

6. PCB Layout¶

6.1 Mechanical and Footprint¶

The module measures 18.0 × 32.9 × 3.1mm. Use the recommended PCB footprint from the datasheet and verify the land pattern, solder-mask expansion, paste opening, keep-out, and assembly courtyard with the PCB assembly vendor.

6.2 Antenna Placement¶

If the product uses the PCB on-board antenna, reserve the antenna area with no components or metal. Place the module so the antenna area extends beyond the carrier-board edge when possible, with the feed point close to the board edge.

If the antenna cannot extend beyond the board edge, provide a clearance area of at least 15mm. Do not place copper, traces, or components in that clearance, and cut away the carrier-board material under the PCB antenna as much as practical.

6.3 External Antenna Connector¶

For external antenna designs, the datasheet describes a first-generation external antenna connector compatible with Hirose U.FL series, I-PEX MHF I, and Amphenol AMC connectors.

6.4 Layout Checklist¶

7. Hardware Validation¶

7.1 Electrical Characteristics¶

VDD is the I/O supply. VOH and VOL are measured with a high-impedance load.

7.2 Power Consumption¶

7.3 Schematic Checklist¶

7.4 Production Handling¶

8. Related Documents¶

Appendices¶

Appendix A. Pin Planning Reference¶

DS5602 V0.3 provides the complete 89-pin definition table and top-view pinout. The table below highlights the pins and signal groups that most often affect schematic risk, boot/debug access, or shared-resource planning.

Appendix B. Revision History¶