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M2 Interface Definition

Draft interface definition

This page records the M2 proposal in the supplied interface-definition workbook. It is a working interface definition, not yet a released μForge.io interface standard. Validate the selected module, carrier, connector, electrical limits, and pin multiplexing before committing a design to production.

Scope

M2 defines a 75-position, M.2 E-key-style connector form. Positions 24–31 form the key, leaving 67 electrical contacts per connector. The workbook provides a base M2 allocation, a multimedia M2xM allocation, and M2xN/M2xA contact maps using the same 67-contact form.

  • M2 — connected display, audio, storage, debug, and general embedded I/O.
  • M2xM — multimedia display, camera, PDM, and I2S/PCM signals.
  • M2xN — networking, USB, CAN, and UART signals.
  • M2xA — motor control, analog acquisition, encoder, and timer signals.

M2xH and M2xP remain naming reservations; the workbook does not assign their contacts.

Connector-model interpretation

The workbook gives both the M2 and M2xM allocations 67 contacts. This page therefore treats M2 as the first connector allocation and M2xM as an optional second connector allocation, rather than as two functions sharing one connector. The mechanical connector count and placement for M2xN and M2xA are still to be frozen.

Connector convention

The pin numbers below use the workbook convention: odd-numbered contacts are on the top side and even-numbered contacts are on the bottom side, viewed from the card edge. Pins 24–31 are absent because of the E-key notch.

M2 Connector and Extension Summary
Item Definition
Connector format 75-position, M.2 E-key-style card edge, 67 electrical contacts per connector
Keyed positions 24–31
Base allocation M2
Multimedia allocation M2xM
Defined extension maps M2xM, M2xN, and M2xA
Declaration example M2 + M2xM

M2 base profile

M2 is the base profile for compact connected products. Its allocation is intended to cover a QSPI display and capacitive touch panel, Wi-Fi SDIO, 1-bit TF-card SDIO, analog audio, debug, USB, CAN, and general buses. Several contacts are intentionally multiplexed so that one module can select the function appropriate to its SoC and product configuration.

M2 Functional Allocation
Function Allocated signals Design intent
Power USB_VIN (listed as VBUS in the workbook summary), VBAT/VBATS, 3.3V, CHG_INT, and GND USB/battery input, regulated module supply, charge status, and return paths.
QSPI display LCDC1_SPI_CS, CLK, DIO0–DIO3, CS2, TE, RSTB, LCD_BL_PWM QSPI display panel, backlight, and optional secondary chip select.
Capacitive touch CTP_I2C1_SDA, CTP_I2C1_SCL, CTP_INT, CTP_REST Capacitive-touch control and interrupt.
Wi-Fi WiFi_SD2_CLK, CMD, D0–D3, PDN, INT, WAKE 4-bit SDIO Wi-Fi companion interface.
TF card TF_SD1_CMD, CLK, D0, TF_DET 1-bit TF-card interface and card detect.
Analog audio ADC_1P/N, ADC_2P/N, MIC_BIAS, DAC_1P/N, DAC_2P/N, AU_PA_EN Two analog-input pairs, microphone bias, two DAC pairs, and PA enable.
Debug and recovery DBG_UART1_TXD/RXD, SWDIO, SWCLK, SWD_SW, BOOT_MODE Debug UART, SWD, and boot/recovery selection.
General serial buses SPI1/SPI2, I2C2–I2C4, UART2/UART3, and general GPIO/bus lines (G0–G17/BUS0–BUS17) Product-specific buses selected through the module pin mux; I2C1 is allocated to the touch controller. Several SPI2/I2C3/I2C4/UART3 positions can alternatively carry PDM1/PDM2 digital-microphone signals.
Other control CAN_TX/RX, USB/USB host signals, PWR_KEY Field bus, USB role control, and power-key input.

Color-coded M2 pinout guide

The colored bar is the table key. The two-sided contact table below is the authoritative M2 pinout, including alternate functions and multiplexing.

M2 contact assignment

This two-sided grid uses Bottom Pin / Top Pin / CN1 columns. The Alt columns record an additional multiplexed function when the workbook assigns one. Every function cell uses its category color from the legend above.

M2 Base Contact Assignment
Alt Function Bot pin CN1 Top pin Function Alt
SDIO2_D2 / GPADC WiFi_SD2_D2 74 75 TF_DET SDIO1_D1 / SPI1_MOSI / UART2_RXD
SDIO2_D3 / GPADC WiFi_SD2_D3 72 73 TF_SD1_D0 SDIO1_D0 / SPI1_MISO / UART2_TXD
SDIO2_CMD / GPADC WiFi_SD2_CMD 70 71 TF_SD1_CLK SDIO1_CLK / SPI1_SCK / UART2_CTS
SDIO2_CLK / GPADC WiFi_SD2_CLK 68 69 TF_SD1_CMD SDIO1_CMD / SPI1_CS# / UART2_RTS
SDIO2_D0 / GPADC WiFi_SD2_D0 66 67 WiFi_WAKE SDIO1_D3 / CAN_RX
SDIO2_D1 / GPADC WiFi_SD2_D1 64 65 WiFi_INT SDIO1_D2 / CAN_TX
GND 62 63 GND
GPADC PWR_KEY 60 61 USBHOST_D−
PDM1_DATA / I2C3_SDA / UART2_RXD / G0/BUS0 SPI2_MISO 58 59 USBHOST_D+
PDM1_CLK / I2C3_SCL / UART2_TXD / G1/BUS1 SPI2_MOSI 56 57 USB_OTG
PDM2_DATA / I2C4_SDA / UART3_RXD / UART2_CTS / G2/BUS2 SPI2_SCK 54 55 CTP_I2C1_SDA G5/BUS5
PDM2_CLK / I2C4_SCL / UART3_TXD / UART2_RTS / G3/BUS3 SPI2_CS# 52 53 CTP_I2C1_SCL G6/BUS6
G4/BUS4 CHG_INT 50 51 CTP_INT G7/BUS7 / SWDIO
USB_VIN 48 49 CTP_REST G8/BUS8 / SWCLK
GND 46 47 GND
3.3V 44 45 VBAT/VBATS
G9/BUS9 USB_DET 42 43 DBG_UART1_TXD SWDIO
G10/BUS10 WiFi_PDN 40 41 DBG_UART1_RXD SWCLK
UART3_RXD G11/BUS11 38 39 G14/BUS14 UART2_RXD
UART3_TXD G12/BUS12 36 37 G15/BUS15 UART2_TXD
I2C2_SCL G13/BUS13 34 35 G16/BUS16 I2C2_SDA
GND 32 33 AU_PA_EN G17/BUS17
E-key notch (24–31) E-key notch (24–31)
DAC_1N 22 23 DAC_2N
DAC_1P 20 21 DAC_2P
ADC_2N 18 19 GND
MIC_BIAS 16 17 ADC_2P
ADC_1N 14 15 ADC_1P
LCDC1_SPI_CS2 12 13 GND
LCDC1_SPI_DIO2 10 11 LCDC1_SPI_DIO3
LCDC1_SPI_DIO0 8 9 LCDC1_SPI_DIO1
LCDC1_SPI_CS 6 7 LCDC1_SPI_CLK
LCD_BL_PWM 4 5 LCDC1_SPI_TE
SWD_SW 2 3 LCDC1_SPI_RSTB
1 BOOT_MODE

M2 pin descriptions

Grouped and colored consistently with the contact table above. The workbook does not define I/O directions; the direction column is therefore an integration aid that must be confirmed against the selected module and SoC documentation.

Signal group Signal I/O Description
Power VBAT/VBATS I Battery-input rail.
Power 3.3V I 3.3 V supply rail.
Power CHG_INT O Charger interrupt / status output.
Power USB_VIN I USB input / charging-path rail.
Power USB_DET I USB detection signal.
Power USBHOST_D+, USBHOST_D− I/O USB host-mode data pair, separate from the primary USB port.
Power USB_OTG I/O USB OTG ID / role-detect signal.
Display LCDC1_SPI_CS, LCDC1_SPI_CS2 O QSPI display primary and optional secondary chip select.
Display LCDC1_SPI_CLK O QSPI display clock.
Display LCDC1_SPI_DIO0DIO3 I/O QSPI display data lines.
Display LCDC1_SPI_TE I Tearing-effect sync input from the panel.
Display LCDC1_SPI_RSTB O Display panel reset, active low.
Display LCD_BL_PWM O Backlight PWM control.
Touch CTP_I2C1_SDA, CTP_I2C1_SCL I/O Capacitive-touch controller I²C bus.
Touch CTP_INT I Touch-controller interrupt.
Touch CTP_REST O Touch-controller reset. The workbook spells this signal CTP_REST.
Wi-Fi / SDIO WiFi_SD2_CLK, WiFi_SD2_CMD O, I/O Wi-Fi companion SDIO clock and command.
Wi-Fi / SDIO WiFi_SD2_D0, WiFi_SD2_D1, WiFi_SD2_D2, WiFi_SD2_D3 I/O Wi-Fi companion SDIO data lines (4-bit).
Wi-Fi / SDIO WiFi_PDN O Wi-Fi module power-down control.
Wi-Fi / SDIO WiFi_INT I Wi-Fi interrupt. Shares pin 65 with SDIO1_D2/CAN_TX.
Wi-Fi / SDIO WiFi_WAKE I/O Wi-Fi wake signal. Shares pin 67 with SDIO1_D3/CAN_RX.
Wi-Fi / SDIO TF_SD1_CMD, TF_SD1_CLK, TF_SD1_D0 I/O, O, I/O 1-bit TF-card SDIO command, clock, and data.
Wi-Fi / SDIO TF_DET I TF-card presence detect.
Wi-Fi / SDIO SDIO1_D0–D3, SDIO2_D0–D3 I/O Generic controller-level aliases for the same physical lines as the TF-card (SDIO1) and Wi-Fi companion (SDIO2) buses; use the role-specific names above unless the module needs full 4-bit SDIO on both sides.
Wi-Fi / SDIO CAN_TX, CAN_RX O, I Logic-level CAN transceiver interface, multiplexed onto pins 65 and 67 alongside WiFi_INT/WiFi_WAKE. The carrier still needs a CAN transceiver and protection appropriate to the product bus.
Wi-Fi / SDIO GPADC I Several Wi-Fi/TF-card and PWR_KEY contacts can alternatively be routed to the ADC for analog sensing.
Audio ADC_1P/N, ADC_2P/N I Two differential analog-microphone input pairs.
Audio MIC_BIAS O Microphone bias supply.
Audio DAC_1P/N, DAC_2P/N O Two differential audio-output pairs.
Audio AU_PA_EN O Audio power-amplifier enable.
SPI / I²C / UART SPI1_CS#, SPI1_SCK, SPI1_MOSI, SPI1_MISO O, O, O, I SPI1, multiplexed with the TF-card path.
SPI / I²C / UART SPI2_CS#, SPI2_SCK, SPI2_MOSI, SPI2_MISO O, O, O, I SPI2, multiplexed with I2C3 and UART2.
SPI / I²C / UART I2C2_SDA, I2C2_SCL I/O, O I2C2, multiplexed with MPI/SD.
SPI / I²C / UART I2C3_SDA, I2C3_SCL I/O, O I2C3, multiplexed with SPI2.
SPI / I²C / UART I2C4_SDA, I2C4_SCL I/O, O I2C4, multiplexed with SPI2 and UART3.
SPI / I²C / UART UART2_TXD/RXD, UART2_CTS/RTS O/I, I/O UART2, multiplexed with SPI2, I2C3, and MPI/SD.
SPI / I²C / UART UART3_TXD/RXD O/I UART3, multiplexed with SPI2, I2C4, and MPI/SD.
SPI / I²C / UART G0–G17/BUS0–BUS17 I/O Generic GPIO/bus contacts, multiplexed with SPI2, I2C2–I2C4, UART2/UART3, PDM1/PDM2, or SWD depending on position.
Audio PDM1_CLK/DATA, PDM2_CLK/DATA I Digital-microphone PDM pairs, multiplexed onto the SPI2/I2C3/I2C4/UART3 contacts (pins 58–52).
Dedicated DBG_UART1_TXD/RXD O/I Debug UART, multiplexed with SWD.
Dedicated SWDIO, SWCLK I/O, I SWD debug port. Two alternative sharing options: the debug-UART positions (pins 43/41) or the capacitive-touch I2C1 positions (pins 51/49). Only one should be populated per module.
Dedicated SWD_SW I Selects SWD vs. debug-UART routing.
Dedicated BOOT_MODE I Boot / recovery mode select.
Dedicated PWR_KEY I Power-key signal.
Ground GND Digital and analog return paths, distributed across the connector.

Wi-Fi SDIO data-label correction

Pin 64 is WiFi_SD2_D1 (an earlier workbook revision mislabeled it as a duplicate of pin 72's WiFi_SD2_D3; this is now corrected). Both SDIO buses also carry generic controller-level aliases in the Alt column — SDIO2_D0–D3/SDIO2_CMD/SDIO2_CLK for the Wi-Fi companion bus, SDIO1_D0–D3/SDIO1_CMD/SDIO1_CLK for the TF-card bus — alongside their role-specific names.

M2 sharing rules

  • The workbook marks SWD as a multiplexed resource with two alternative routing options: the debug-UART positions (SWDIO on pin 43, SWCLK on pin 41) or the capacitive-touch I2C1 positions (SWDIO on pin 51, SWCLK on pin 49). Populate only one option per module and reserve a recovery strategy before reusing any of these contacts.
  • SPI1 is shared with the 1-bit TF-card path; both are also exposed as the generic SDIO1_D0–D3/CMD/CLK controller bus, and pins 65/67 additionally carry CAN_TX/CAN_RX.
  • The Wi-Fi SDIO2 data lines are also exposed as the generic SDIO2_D0–D3/CMD/CLK controller bus; several of the same contacts double as GPADC analog inputs.
  • SPI2 and I2C3/I2C4 (pins 58–52) can alternatively carry PDM1/PDM2 digital-microphone signals, plus generic G0–G3/BUS0–BUS3 GPIO aliases.
  • I2C2–UART3 share the same six positions (pins 38–34/39–35), which also carry generic G11–G16/BUS11–BUS16 GPIO aliases when not used for a named bus function.
  • The QSPI display and capacitive-touch groups are separate at the signal level, but their power, reset, and wake behavior must be reviewed as one display subsystem.
  • CAN_TX and CAN_RX are logic-level signals multiplexed onto pins 65/67, not separately allocated contacts. The carrier still needs a CAN transceiver and protection appropriate to the product bus.

M2xM multimedia profile

M2xM defines the multimedia connector allocation for display, camera, and digital-audio designs. It defines interface groups rather than asserting that every module can operate every group concurrently.

M2xM Functional Allocation
Function Workbook allocation Sharing rule
RGB / 8080 / EPD display RGB timing plus R0–R7, G0–G7, B0–B7; 8080 and EPD controls 31 contacts; DBI/8080 and EPD share the display allocation.
MIPI DSI D0–D3 differential lanes, clock pair, TE, reset, I2C, backlight PWM Reuses the RGB allocation and adds six GND contacts.
Capacitive touch I2C, interrupt, and reset Shares the QSPI-display allocation.
12-bit DVP camera D0–D11, MCLK, PCLK, HSYNC, VSYNC, PWDN, reset, I2C4 20 contacts; includes the workbook's QSPI interface allocation.
MIPI CSI D0/D1 differential lanes, clock pair, PWDN, reset, I2C Reuses the DVP allocation and adds four GND contacts.
Digital microphones PDM1_CLK/DATA and PDM2_CLK/DATA Four PDM signals.
I2S / PCM I2S2_BCK, LRCK, SDI, SDO Shares the digital-audio contacts.

The workbook labels MIPI DSI and MIPI CSI as alternative signal maps. Those labels do not, by themselves, establish support on a particular μForge module or SoC package; confirm device capability and routing requirements in the selected module documentation.

M2xN networking profile

M2xN is the networking-oriented extension map. It assigns one 67-contact M2-form connector to Ethernet, dual USB, CAN, UART, reserved GPIO, and GND.

M2xN Functional Allocation
Function Allocated signals
Ethernet The workbook summary calls this Gigabit Ethernet / RGMII, while its contact map labels the signals RMII_*. Resolve this naming conflict before implementation.
USB USB1_D±, USB1_DET, USB1_OTG, USB2_D±, USB2_DET, USB2_OTG
CAN CAN1_TX/RX through CAN4_TX/RX, plus CAN1/2_STB and CAN1/2_ERR_N controls where assigned
UART UART1_TX/RX/CTS/RTS and UART2_TX/RX/CTS/RTS
Reserved 15 GPIO contacts and 12 GND contacts

M2xA analog and motion-control profile

M2xA is the motor-control and acquisition extension map. It assigns one 67-contact M2-form connector to complementary PWM outputs, analog inputs, motor-driver control, Hall/encoder inputs, timer channels, reserved GPIO, and dedicated grounds.

M2xA Functional Allocation
Function Allocated signals
BLDC control PWM1_OUT/OUTN, PWM2_OUT/OUTN, PWM3_OUT/OUTN, BKIN1/2, DRV_EN, and DRV_NFAULT; the summary labels five analog inputs as ADC_IU/V/W, ADC_VBUS, and ADC_NTC, while the contact map labels them ADC_IN1–ADC_IN5.
Position feedback H_A, H_B, H_C, ENC_A, ENC_B, ENC_Z
General timing TIM_CH1–TIM_CH6
Reserved 27 GPIO contacts and 13 GND contacts

Module declaration and implementation checklist

A module declaration should identify its base allocation and each supported extension map, for example M2, M2 + M2xM, or M2 + M2xN + M2xA. It should state the number of M2-form connectors implemented, their category, the implemented optional functions, and any mutually exclusive modes.

Before adopting this draft, verify:

  • The M.2 E-key connector footprint, card outline, retention hardware, and insertion orientation.
  • The number, placement, and category of M2-form connectors on the module and carrier.
  • All multiplexed functions selected by the module, including any shared SDIO1/SDIO2, PDM, SWD (debug-UART vs. CTP I2C1), or CAN routing.
  • Module-specific I/O voltage, current, reset, boot, and power-sequencing requirements.
  • Whether a claimed M2xM MIPI, RGB, DVP, PDM, or I2S function is supported simultaneously or only as an alternate mode.
  • Carrier-side requirements for CAN transceivers, USB protection, TF-card power/detect, display power, audio amplification, and external PHYs.