SF32LB52x Hardware Design Guide¶

1. Introduction¶

This hardware design guide provides design recommendations and source-backed reference material for products based on the SF32LB52x family of ultra-low-power AIoT microcontrollers. It is intended for hardware engineers, PCB designers, and product developers building battery-powered wearable devices and other compact embedded systems.

The guide covers the complete hardware development process, including power-supply design, clock circuits, RF layout, display and storage interfaces, audio circuits, PCB layout recommendations, and manufacturing considerations. Following these guidelines helps reduce development risk, improve system reliability, and shorten the product development cycle.

This document assumes a basic understanding of embedded hardware design and schematic capture. It complements the SF32LB52x datasheet, reference manual, and SDK documentation, which remain the authority for detailed electrical specifications, peripheral operation, and software development.

It consolidates two original SiFli hardware application notes — one for the battery-powered SF32LB520/3/5/7 path and one for the externally regulated 52B/D/E/G/J path — into a single engineering workflow. Where the original source wording is inconsistent, this guide favors exact orderable part numbers, explicit supply-domain behavior, and release-review clarity.

2. Development Resources¶

3. Device Overview¶

The SF32LB52x family combines dual-core STAR-MC1 processors, Bluetooth connectivity, graphics acceleration, integrated audio, display interfaces, storage controllers, and power management in a compact QFN68 package. The family is optimized for products where BOM cost, battery life, and PCB area all matter.

3.1. Features¶

The family integrates:

• Dual-core Arm China STAR-MC1 processors with FPU and MPU, Arm Cortex-M33 compatible
• Dual-mode Bluetooth 6.3 radio
• ePicasso 2.0 2D/2.5D graphics accelerator
• Display controller supporting SPI, QSPI, 8080, JDI, and 8-bit EPD interfaces
• USB 2.0 Full-Speed device
• SDIO/eMMC storage interface on supported variants
• Analog and digital audio interfaces
• Integrated PMU, DC/DC converter, and LDO regulators
• QFN68 package with up to 44/45 GPIOs

3.2. Variants¶

The SF32LB52x family is divided into two practical design groups by power architecture: battery-powered devices and externally regulated devices, as shown below.

3.3. Packages¶

Both design groups use the same QFN68 package.

The two design groups differ slightly in peripheral resources. The battery-powered group has 44 GPIOs, while the regular-powered group has 45 GPIOs; the difference comes from pins reserved for charging on the battery-powered devices.

• 44/45 GPIOs
• 3x UART
• 4x I2C
• 2x GPTIM
• 2x SPI
• 1x I2S audio interface
• 1x SDIO storage interface
• 1x PDM audio interface
• 1x differential analog audio output
• 1x single-ended analog audio input
• Single/dual/quad-data-line SPI display interface, serial JDI display interface
• Supports displays both with and without GRAM
• Supports UART download and software debug

The pin layout diagrams are shown below, and their differences will be revisited in the schematic design section.

3.4. Applications¶

Typical applications are portable embedded systems where long battery life and compact form factors are essential. Examples include:

• Entry-level smartwatches and fitness bands
• Bluetooth modules and wireless adapters
• Bluetooth audio accessories
• Smart sensors and wearable devices
• Electronic shelf labels and smart badges
• E-book readers
• Portable label printers
• eBike and eScooter displays
• Connected human-machine interface (HMI) devices
• Portable industrial and medical equipment
• Other battery-powered AIoT devices

4. Design at a Glance¶

4.1. Hardware Architecture¶

The following table summarizes the recommended hardware architecture for a typical SF32LB52x application. Use it as a quick reference before reading the detailed design guidance in the later sections.

4.2. Hardware Design Flow¶

Follow the guide in the order that hardware decisions typically get locked in. The flow below keeps early architecture choices visible before the design moves into schematic and PCB details.

Design decision tree

• Need USB-rechargeable single-cell battery operation? Start with SF32LB520/3/5/7.
• Need an externally regulated supply or eMMC boot? Start with 52B/D/E/G/J.
• Need 8-bit parallel EPD? Use the regular-powered design path unless SiFli confirms the battery-powered path for the exact design.
• Need the lowest standby current? Decide storage power switching, sensor load switches, and display power isolation before PCB placement.

4.3. How to Use This Guide¶

Start with the exact orderable part number before schematic work begins, because the SF32LB52x family splits into two practical design groups: the battery-powered SF32LB520/3/5/7 group and the externally regulated 52B/D/E/G/J group. Use Section 3.2 to select the group, Sections 5.1 and 5.2 to complete the minimum-system and power-system reviews, Sections 5.6.1 and 5.7.1 to verify boot storage and debug access, Sections 5 and 6 to review schematic and PCB guidance, Appendices A-E to compare the source reference figures, and Section 7 as the release checklist.

When a design reuses an older SF32LB52x schematic, review the supply pins, SIP-memory supply, boot-storage rail, DBG_UART/SWD pins, crystal loading, RF matching footprint, and production test points first. Those items are the most common sources of silent bring-up risk.

4.4. Review Evidence Pack¶

Before hardware release, collect the schematic PDF, PCB stack-up, impedance report, component AVL cross-check, DRC report, and screenshots of the RF, crystal, USB, SDIO/eMMC, audio, power, and boot-storage layouts. Keep the evidence with the board revision so later firmware, RF, and production issues can be traced back to the reviewed hardware baseline.

5. Schematic Design Guidelines¶

This chapter follows the schematic workflow. Complete the minimum-system review first, then expand into clock generation, RF, user interfaces, storage, manufacturing access, and PCB-dependent decisions. For each major block, confirm the design goal and variant scope before checking circuit requirements, pin assignment, common mistakes, and release checklist items.

5.1. Minimum System Design¶

Minimum system design is the first schematic release gate for an SF32LB52x board. It covers the decisions that must be correct before product peripherals are added: exact device variant, package, power tree, boot medium, bootstrap resistors, storage power control, debug/download access, clock sources, and wake behavior. A board can often tolerate late changes to display or sensor wiring; it usually cannot tolerate a wrong storage strap, missing debug access, unstable rail, or incompatible power-state assumption.

Use the following sequence for the first schematic pass:

1. Select the exact device and package from Section 3.2 and Section 3.3.
2. Choose the correct power path: SF32LB520/3/5/7 for rechargeable battery-powered products, or 52B/D/E/G/J for externally regulated products.
3. Lock the power-system decisions in Section 5.2, including VBUS/VBAT/VCC or PVDD/VDDIOA/VDD_SIP, BUCK, internal LDO decoupling, RF/audio rails, and all low-power load switches.
4. Select the boot medium and populate PA13/PA17 bootstrap pull options to match the boot table in Section 5.6.1.
5. Route all boot-storage power switches to PA21, including large NOR Flash designs that must exit 4-byte mode after restart or Hibernate.
6. Reserve PA18/PA19, ground, and a valid power reference for DBG_UART/SWD access before the enclosure and production fixture are frozen.
7. Select the 48 MHz and 32.768 kHz crystals from Section 5.3.1 and keep their placement constraints visible during schematic review.
8. Assign wake pins, power-key behavior, charger events, and storage/sensor shutdown states before firmware low-power policy is finalized.

At the end of this gate, the schematic should be able to power up, boot from the selected medium, expose a recovery path, run clock calibration, and enter the intended low-power state without relying on optional product peripherals.

5.2. Power System¶

Power-system design defines the rails, load switches, charger path, OVP, internal LDO usage, wake behavior, and low-power states that make the minimum system reliable. Complete this section before PCB placement, because later display, storage, RF, audio, and sensor decisions depend on these rail assumptions.

5.2.1. Power Supply¶

Quick Summary

• Battery-powered devices use the SF32LB520/3/5/7 path with VBUS, VBAT, VCC, charging, and OVP decisions.
• Regular-powered devices use the 52B/D/E/G/J path with externally regulated PVDD, VDDIOA, VDD_SIP, and no internal charging path.
• BUCK inductor, internal LDO decoupling, RF/audio rails, and standby load switches must be fixed before PCB placement.

Design Goal

Create a stable, low-leakage power tree that supports the selected variant, avoids overloading internal LDO outputs, keeps RF and audio rails quiet, and allows unused loads and boot storage to be switched off in low-power modes.

5.2.1.1. Processor Power Supply Requirements¶

5.2.1.2. BUCK Inductor Selection¶

Both design groups use the same inductor specification.

5.2.1.3. Battery and Charging Control¶

5.2.1.4. Reducing Standby Power¶

5.2.1.5. Power Design Checklist¶

• Confirmed which power variant (battery-powered / regular-powered) matches the exact chip model
• BUCK inductor meets 4.7 uH ±20%, DCR ≤0.4 Ω, Isat ≥450 mA
• All internal LDO decoupling capacitors are placed per requirements
• LCD power is isolated and not fed directly from the internal LDO
• Audio and RF power rails are properly filtered
• Battery-powered variant: charging path and OVP device voltage ranges verified; regular-powered variant: VDD_SIP/VDDIOA supply configured correctly for the chip model

Common Mistakes - Power

• Powering the LCD directly from an internal LDO instead of an external LDO.
• Mixing battery-powered and regular-powered supply assumptions in the same schematic.
• Leaving VDD_SIP powered during Hibernate on variants where storage leakage is a risk.
• Choosing a charger or OVP device without verifying the worst-case VBUS current and voltage range.

Bring-Up Checks - Power

• Measure VCC/PVDD, BUCK output, RF/audio rails, and storage supply before firmware enables peripherals.
• Confirm charger attach, trickle charge, constant-current charge, and recharge behavior on battery-powered designs.
• Measure standby and Hibernate current with display, sensors, storage, and motor load switches off.

5.2.2. Operating Modes and Wake Sources¶

Quick Summary

• Active and Sleep retain fast interrupt response; DeepSleep and Standby trade wake time for lower current.
• Hibernate is the lowest-power state, but SRAM is not retained and some external supplies must be shut down.
• Wake-capable GPIO selection affects buttons, touch interrupt, charger events, and sensor wake behavior.

Design Goal

Select wake sources and external power-switch defaults so the product can enter the intended low-power state without leakage paths or missing wake events.

The whole family supports 15 wake-capable interrupt sources in Standby and Hibernate modes:

Operating-Mode Checklist

• Required wake pins are assigned before pin-mux is frozen.
• Pull states on wake pins are compatible with Standby and Hibernate.
• External storage and sensor supplies do not leak through I/O pins in Hibernate.
• Firmware and hardware teams agree which state is used for shipping, shelf, and normal standby modes.

5.3. Clock Generation¶

5.3.1. Crystal Selection¶

Quick Summary

• Use a 48 MHz main crystal and a 32.768 kHz RTC crystal.
• Favor low CL and low ESR parts from the AVL to reduce startup and static current.
• Keep crystal traces short, shielded, and away from heat, RF, charger, PMU, and DC/DC noise.

Design Goal

Provide stable, low-jitter clock sources while minimizing oscillator current, frequency drift, RF interference, and bring-up risk.

The chip requires two external clock sources: a 48 MHz main crystal and a 32.768 kHz RTC crystal. Requirements are identical for both variants.

Recommended crystals:

For the complete, continuously maintained qualification data, refer to the SiFli Approved Vendor List.

Common Mistakes - Clock

• Selecting a crystal only by frequency and package, without checking CL, ESR, tolerance, and temperature range.
• Placing the crystal near PA, charger, PMU, RF matching, or other heat/noise sources.
• Leaving copper or high-speed routing under the crystal keep-out region.
• Making 32 kHz traces long and parallel without spacing or ground shielding.

Clock Checklist

• 48 MHz and 32.768 kHz crystals match AVL/datasheet requirements.
• Crystal load capacitance and ESR are verified against the oscillator limits.
• Keep-out, trace length, trace width, spacing, and ground shielding are checked in PCB review.
• Bring-up plan includes measuring 48 MHz, 32 kHz, and Bluetooth frequency calibration behavior.

5.4. RF¶

5.4.1. RF Schematic and Antenna Path¶

Quick Summary

• Route the antenna path as a 50 Ω controlled-impedance trace.
• Reserve a π matching network even if the selected antenna is already matched.
• Keep the RF path short, shielded, and isolated from crystal, DC/DC, display, and charger noise.

Design Goal

Maximize Bluetooth sensitivity and radiated performance by preserving impedance control, minimizing discontinuities, and leaving enough matching flexibility for final antenna tuning.

RF trace characteristic impedance is 50 Ω. If the antenna is already matched, no additional RF components are required, but a reserved π-type matching network is still recommended for spurious filtering or antenna tuning.

5.4.2. RF Review and Tuning¶

Common Mistakes - RF

• Placing the matching network near the antenna instead of close to the chip-side RF pin.
• Routing RF through unnecessary vias or sharp bends.
• Sharing noisy ground return paths with DC/DC, display, USB, or charger circuits.
• Omitting the matching reserve and leaving no practical antenna-tuning path.

RF Checklist

• RF trace impedance target is defined with the PCB vendor.
• Pi matching network is reserved and placed close to the chip.
• Ground-via fence and RF keep-out are reviewed.
• Antenna tuning and certification access are planned before enclosure freeze.

5.5. User Interfaces¶

5.5.1. Display¶

Quick Summary

• Supported interfaces include SPI, Dual-SPI, Quad-SPI, serial JDI, and EPD on supported regular-powered variants.
• Maximum documented display resolution is 512 x 512.
• Reset, TE, backlight PWM, touch I2C, touch interrupt, and display power sequencing should be reviewed together.

Design Goal

Select a display interface that meets bandwidth and power targets while preserving wake, reset, backlight, and touch behavior across normal operation and low-power states.

The chip supports 3-Line SPI, 4-Line SPI, Dual-data SPI, Quad-data SPI, and serial JDI interfaces, with 16.7M-color (RGB888), 262K-color (RGB666), 65K-color (RGB565), and 8-color (RGB111) depth modes, up to 512x512 resolution.

Supported LCD driver models:

5.5.1.1. SPI/QSPI Display Interface¶

5.5.1.2. JDI Display Interface¶

5.5.1.3. EPD Display Interface¶

5.5.1.4. Touch and Backlight Interface¶

The SF32LB52x supports an I2C touch-controller interface with a touch-status interrupt input, plus one PWM signal for backlight enable and brightness control.

Common Mistakes - Display

• Forgetting reset, TE, backlight PWM, or touch interrupt pins during pin assignment.
• Assuming EPD support on the battery-powered variant without confirming the actual device and source design.
• Powering the display from an internal LDO rather than an appropriately sized external rail.
• Routing display clocks and data beside crystal, RF, audio, or high-impedance analog nodes.

Display Checklist

• Display interface, color depth, resolution, and bandwidth match the selected panel.
• Reset, TE, backlight PWM, touch I2C, and touch interrupt are assigned and documented.
• Display power rail and sequencing are compatible with standby and wake behavior.
• Bring-up plan covers reset, panel ID/readback where available, backlight, touch interrupt, and first image.

5.5.2. Audio Interface¶

Quick Summary

• The analog microphone input is single-ended and requires a DC-blocking capacitor.
• The DAC output is differential and should be routed as a short, shielded differential pair.
• Audio power filtering and MIC_BIAS placement strongly affect noise performance.

Design Goal

Preserve analog signal quality by keeping microphone, DAC, bias, and audio power paths short, filtered, shielded, and isolated from digital and switching-noise sources.

The shared audio interface provides:

1. One single-ended ADC input for an analog microphone, with a DC-blocking capacitor of at least 2.2 uF in series; the microphone is powered from the chip's MIC_BIAS output
2. One differential DAC output for an external audio PA — route as a differential pair with proper ground shielding; keep trace capacitance < 10 pF and length < 2 cm

Common Mistakes - Audio

• Routing microphone or DAC traces near display clocks, DC/DC, RF, USB, or SDIO.
• Placing MIC_BIAS or AVDD33_AUD filter capacitors far from the chip pins.
• Treating DACP/DACN as independent single-ended signals instead of a differential pair.
• Allowing high parasitic capacitance or long trace length on the analog output.

Audio Checklist

• MIC_BIAS, ADCP, DACP, and DACN component placement is reviewed against the layout examples.
• DACP/DACN are routed as a short, shielded differential pair.
• Audio filter capacitors are close to their pins and grounded cleanly.
• Bring-up plan covers microphone bias, ADC noise floor, DAC output, PA enable, and audible noise.

5.5.3. Buttons¶

Quick Summary

• PA34 supports the power button, power on/off behavior, and long-press reset.
• Rotary encoder buttons should follow the reference circuit and be reviewed together with wake, debounce, and ESD requirements.

Design Goal

Provide reliable user-input and reset behavior without false wake events, stuck reset states, or high standby leakage through pull networks.

5.5.3.1. Power Button¶

PA34 supports long-press reset and can be designed as a combined power on/off and long-press-reset button. The long-press reset function is active-high, so the default state should be pulled low and driven high when the button is pressed.

5.5.3.2. Mechanical Rotary Encoder Button¶

Use the reference design as the baseline for the rotary encoder button circuit.

Common Mistakes - Buttons

• Leaving PA34 floating or biased to the wrong default level.
• Forgetting that button circuits may need wake, ESD, debounce, and production-test access.
• Sharing button nets with noisy or heavily loaded functions without checking wake reliability.

Button Checklist

• Power/long-press-reset default level is correct.
• Wake behavior is verified for the intended low-power states.
• ESD and mechanical debounce requirements are reviewed.
• Bring-up plan includes short press, long press, wake, and reset behavior.

5.5.4. Vibration Motor¶

Quick Summary

• Use a PWM output to drive the vibration motor through an external driver stage.
• Power the motor from a switchable rail where standby current matters.

Design Goal

Deliver repeatable haptic feedback while keeping motor surge current, switching noise, and standby leakage away from sensitive rails and wake circuits.

The SF32LB52x supports a PWM output for driving a vibration motor through an external driver stage.

Motor Checklist

• Motor driver, flyback/ESD protection, and supply current rating are reviewed.
• Motor rail default state is off in standby and shipping states.
• PWM pin assignment does not conflict with display, storage, or debug pins.
• Bring-up plan covers PWM duty sweep, start current, audible noise, and standby leakage.

5.6. Storage and Connectivity¶

5.6.1. Storage¶

Quick Summary

• External boot options include SPI NOR, SPI NAND, SD NAND, and eMMC on supported regular-powered variants.
• Bootstrap pins PA13 and PA17 select the boot medium.
• Boot storage power switching uses PA21; incorrect storage power behavior can block restart or increase Hibernate leakage.

Design Goal

Choose a boot medium and storage power architecture that support firmware size, update strategy, low-power states, and reliable ROM boot after reset or Hibernate.

5.6.1.1. Storage Interface Description¶

The chip supports external SPI NOR Flash, SPI NAND Flash, and SD NAND Flash. eMMC is supported only on the 52B/D/E/G/J regular-powered variant.

5.6.1.2. Boot Configuration¶

5.6.1.3. Boot Storage Power Control¶

The chip supports power-switching the boot storage medium to reduce shutdown power. The switch enable pin must be controlled through PA21, active high (on), inactive low (off).

Common Mistakes - Storage

• Missing bootstrap resistors or populating them for the wrong boot medium.
• Leaving PA21 disconnected from the boot-storage power switch.
• Treating eMMC as available on all variants.
• Keeping large NOR Flash always powered when 4-byte mode can break ROM recognition after restart.

Storage Checklist

• Boot medium is selected and documented before PCB layout.
• PA13/PA17 bootstrap pull options match the boot table.
• PA21 controls all required boot-storage power switches.
• eMMC VCC/VCCQ tradeoff is reviewed for regular-powered designs.
• Bring-up plan covers boot-mode strapping, storage rail timing, ID read, and firmware download.

5.6.2. Sensors¶

Quick Summary

• Sensors typically connect through I2C or SPI and should be power-gated when low standby current is required.
• Wake-capable sensor interrupts must be assigned before pinout freeze.

Design Goal

Keep sensor power, interrupt, and bus routing reliable while allowing unused sensors to shut down cleanly in low-power modes.

The SF32LB52x can connect to heart-rate, accelerometer, geomagnetic, and similar sensors. Choose a load switch with low Iq for sensor power switching.

Sensor Checklist

• Sensor bus, interrupt, reset, and power-enable pins are assigned.
• Sensor load switch Iq and shutdown current match the standby target.
• Pull-ups are placed on the correct sensor I/O voltage rail.
• Bring-up plan covers bus scan, interrupt wake, and sensor power cycling.

5.6.3. UART and I2C Pin Assignment¶

Quick Summary

• UART and I2C functions can be mapped to arbitrary PA pins.
• Pin choices should still account for boot, wake, debug, production test, and board routing constraints.

Design Goal

Use flexible pin mapping to simplify routing without blocking required boot straps, wake pins, debug access, or production fixtures.

The SF32LB52x supports UART and I2C function mapping on arbitrary PA pins.

UART/I2C Checklist

• Pull-ups, voltage domains, and bus capacitance are correct for every I2C bus.
• UART pins needed for logs, download, or external modules are accessible.
• Pin multiplexing does not conflict with bootstrap, wake, display, storage, or debug functions.

5.6.4. GPTIM Pin Assignment¶

Quick Summary

• GPTIM functions can be mapped to arbitrary PA pins.
• Timer outputs are commonly used for PWM, capture, motor control, backlight, or product-specific timing.

Design Goal

Reserve timer-capable functions early enough that PWM, capture, and timing features are not forced onto poor routing or wake-conflicting pins late in the design.

The SF32LB52x supports GPTIM function mapping on arbitrary PA pins.

GPTIM Checklist

• Timer channels required for PWM, capture, or control loops are listed in the pinout table.
• GPTIM pins do not conflict with backlight, motor, debug, or storage requirements.
• Bring-up plan includes checking PWM frequency, duty range, and pin polarity.

5.7. Manufacturing¶

5.7.1. Debug and Download Interface¶

Quick Summary

• PA18 and PA19 default to DBG_UART after power-up and are multiplexed with SWD.
• Reserve physical access to the debug/download pins on every prototype and production board.

Design Goal

Guarantee firmware download, debug logs, single-step debug, and failure recovery access even after the product enclosure and production fixture are defined.

The SF32LB52x supports a DBG_UART interface for download and debug, connected to a PC through a 3.3 V UART-to-USB dongle board. SWD and DBG_UART are multiplexed on PA18 and PA19; the default power-on configuration is DBG_UART, which supports single-step debugging as well as log output.

Debug Checklist

• PA18/PA19, ground, and the required power reference are exposed on test pads or connector pins.
• Debug access remains available after enclosure, battery, and display assembly.
• UART voltage level is 3.3 V compatible with the selected adapter or fixture.
• Recovery path is documented for a board that cannot boot application firmware.

5.7.2. Production Flashing and Crystal Calibration¶

Quick Summary

• Production programming and crystal calibration require stable power, DBG_UART access, PA01, and the required power/ground test points.
• Fixture access should be designed before the PCB mechanical outline and enclosure are frozen.

Design Goal

Make every production board programmable, calibratable, and recoverable without manual soldering or product disassembly.

SiFli provides an offline downloader for production firmware flashing and crystal calibration. Reserve at least these test points in the hardware design: PVDD/VBAT, GND, AVDD33, DBG_UART_RXD, DBG_UART_TXD, and PA01. See the "Offline Downloader User Guide" document included in the development package for the detailed flashing and calibration process.

Production Checklist

• PVDD/VBAT, GND, AVDD33, DBG_UART_RXD, DBG_UART_TXD, and PA01 test points are reserved.
• Test pads are reachable by the intended fixture after mechanical assembly.
• Crystal calibration flow and pass/fail limits are defined with manufacturing.
• Programming, calibration, and functional-test records can be tied back to the board revision.

5.7.3. Schematic and PCB Drawing Checklists¶

Use the official schematic and PCB checklist published on SiFli's wiki as the formal release gate — see the SF32LB52x Hardware Design Checklist for the complete, item-by-item version. The local checklists in this guide are intended to catch common engineering issues before the formal checklist review.

Release Checklist

• Schematic checklist, PCB checklist, AVL check, DRC report, and impedance report are complete.
• Evidence screenshots are archived for power, clock, RF, display, storage, audio, USB, SDIO, DC/DC, and production-test access.
• Variant-specific assumptions are documented in the review notes.
• Open hardware risks are assigned to an owner before release.

6. PCB Layout Guidelines¶

Use this chapter as the layout-review companion to Section 5. The schematic should already define the variant, power tree, clock parts, RF reserve, display/storage pins, and test access before final placement begins.

Design Goal

Translate the schematic into a manufacturable 4-layer PTH board while protecting the sensitive RF, crystal, audio, power, USB, and SDIO paths from impedance, noise, and return-current problems.

PCB Review Flow

1. Confirm package footprint and paste/land pattern.
2. Confirm stack-up, trace/space, drill, and impedance rules with the PCB vendor.
3. Place chip, crystals, RF path, DC/DC, charger, display/storage connectors, and audio components.
4. Review fanout and sensitive routing before filling less critical GPIO routes.
5. Capture evidence screenshots for RF, crystals, USB, SDIO, audio, DC/DC, charger, and power rails.

6.1. PCB Footprint Design¶

The SF32LB52x QFN68L package is 7 mm x 7 mm x 0.85 mm, with 68 pins and 0.35 mm pitch.

6.2. PCB Stack-Up¶

The reference design supports single- or double-sided placement. Components can be placed on one side, or capacitors and similar passives can be placed on the back side under the chip. A 4-layer through-hole via (PTH) stack-up is recommended.

6.3. General PCB Design Rules¶

Follow the general PTH-board PCB design rules from the reference design.

6.4. PCB Trace Fanout¶

Fan out all QFN package signals through the top layer.

6.5. Clock Interface Routing¶

Apply these clock-routing rules across both design groups:

• Place crystals inside the shield can, more than 1 mm from the PCB edge, and as far as practical from heat-generating components (PA, charger, PMU circuits) — ideally more than 5 mm — to avoid affecting crystal frequency drift
• Keep the crystal keep-out zone larger than 0.25 mm, free of other metal or components
• Route 48 MHz crystal traces on the top layer, 3–10 mm long, 0.1 mm wide, with full ground shielding, away from VBAT/VCC, DC/DC, and high-speed signal lines; keep the top layer and adjacent layer under the crystal area clear of other routing
• Route 32.768 kHz crystal traces on the top layer, ≤10 mm long, 0.1 mm wide, with ≥0.15 mm spacing between the parallel 32K_XI/32K_XO traces, and full ground shielding

6.6. RF Interface Routing¶

Apply these RF-routing rules across both design groups:

• Place the RF matching circuit close to the chip side, not the antenna side
• Place the AVDD_BRF filter capacitor close to the chip pin, with its ground pin vias connected directly to the main ground
• Route RF traces on the top layer where possible, avoiding vias that would hurt RF performance; keep trace width above 10 mil with full ground shielding, and avoid acute or right-angle bends
• Control RF trace impedance to 50 Ω, with dense shielding ground vias along both sides

6.7. Audio Interface Routing¶

Apply these audio-routing rules across both design groups:

• Place the AVDD33_AUD filter capacitor close to its pin; place the MIC_BIAS filter capacitor close to its pin
• Keep components for the ADCP analog input close to the chip pin, with short traces, full ground shielding, and away from other strong interference sources
• Keep components for the DACP/DACN analog output close to the chip pin, routed as a differential pair, with short traces, parasitic capacitance below 10 pF, and full ground shielding

6.8. USB Interface Routing¶

Route USB DP (PA35) / DN (PA36) through the ESD device pins first, then to the chip, and ensure the ESD device ground connects solidly to the main ground. Route the pair with 90 Ω differential impedance control and full ground shielding.

6.9. SDIO Interface Routing¶

Route SDIO signals together as a group, with total trace length ≤50 mm and within-group length matching ≤6 mm. Provide full ground shielding for the clock signal, and shield the DATA and CMD signals as well.

6.10. DC/DC Circuit Routing¶

Place the power inductor and filter capacitors close to the chip pins. Keep the BUCK_LX trace short and wide, and keep the BUCK_FB feedback trace no thinner than 0.25 mm. Connect all DC/DC output filter capacitor ground pins to the main ground plane with multiple vias. Do not pour top-layer copper in the power inductor area, and keep the adjacent layer as a complete reference ground.

6.11. Power Supply Routing¶

6.12. Other Interface Routing¶

Pins configured as GPADC inputs must have full ground shielding and must stay away from interference sources such as battery-level sensing and temperature-detection circuits.

6.13. EMI & ESD¶

Apply these EMI and ESD rules across both design groups:

• Avoid long top-layer traces outside the shield can, especially for clock and power interference sources — route them on inner layers where possible
• Place ESD protection devices close to the connector pins, routing signals through the ESD device before anything else
• Ensure ESD device ground pins connect to the main ground through vias, with short and wide ground pad traces to reduce impedance and improve ESD performance

6.14. Other Considerations¶

Place USB charging-line test points before the TVS diode, and place the battery-holder TVS diode before the platform connection. Route the signal so it always passes through the TVS before reaching the chip. Keep TVS ground-pin traces as short as possible.

7. Design Review Checklist¶

• Minimum-system review is complete: exact variant, package, power tree, boot medium, bootstrap pins, debug/download access, clocks, and wake strategy are all documented
• The exact chip model and power variant are confirmed, and power schematics from the two variants are not mixed
• Processor power pins (VBUS/VBAT/VCC, or PVDD/VDDIOA/VDD_SIP) are within the datasheet voltage range
• BUCK inductor meets 4.7 uH ±20%, DCR ≤0.4 Ω, Isat ≥450 mA
• Battery-powered variant: charging path, OVP device voltage range, and integrated-LDO output capacitance are verified
• 48 MHz and 32.768 kHz crystals meet the recommended specifications, with routing and keep-out zones satisfied
• RF trace is 50 Ω impedance, with the matching network placed close to the chip
• Storage boot configuration (including the regular-powered variant's eMMC option) matches the Bootstrap pin settings
• Storage power switches are uniformly controlled through PA21, active high (on) / low (off)
• USB and SDIO differential trace impedance and length matching meet requirements
• DBG_UART/SWD multiplexed pins and production test points are reserved
• Key component part numbers have been verified against the latest SiFli Approved Vendor List

8. Related Documents and References¶

Additional source references:

• SF32LB52x Product Brief
• SF32LB52x Datasheet
• SF32LB52x Reference Manual
• SF32LB520/3/5/7 Hardware Application Note
• 52B/D/E/G/J Hardware Application Note

9. Appendices¶

The original SiFli application notes include the following schematic, PCB layout, mechanical, and power reference figures. These appendices preserve those source figures for review evidence, while Sections 5 and 6 remain the primary design guidance.

Appendix A. A Typical Smart Watch Application¶

A typical SF32LB52x smart watch design includes the MCU, display, touch controller, storage, sensors, vibration motor, audio input/output, Bluetooth antenna, clock sources, power management, debug access, and production-test access. The battery-powered design additionally includes charging management.

Appendix B. Reference Schematics¶

RF

Storage and Boot

Buttons, Motor, and Audio

Clock

USB

DC/DC

Appendix C. Reference PCB Layouts¶

RF

Storage

Audio

PCB Foundation

Clock Routing

USB

DC/DC

Appendix D. Mechanical¶

Appendix E. Power¶

SF32LB520/3/5/7 (Battery-Powered)

52B/D/E/G/J (Regular-Powered)

10. Revision History¶