SF32LB52x Hardware Design Guide — Schematic Design Guidelines¶

5. Schematic Design Guidelines¶

This chapter follows the schematic workflow across three pages. Complete the minimum-system review first, then expand into clock generation on this page; RF and user interfaces on the next page; and storage, manufacturing access, and PCB-dependent decisions on the final page. For each major block, confirm the design goal and variant scope before checking circuit requirements, pin assignment, common mistakes, and release checklist items.

5.1. Minimum System Design¶

Minimum system design is the first schematic release gate for an SF32LB52x board. It covers the decisions that must be correct before product peripherals are added: exact device variant, package, power tree, boot medium, bootstrap resistors, storage power control, debug/download access, clock sources, and wake behavior. A board can often tolerate late changes to display or sensor wiring; it usually cannot tolerate a wrong storage strap, missing debug access, unstable rail, or incompatible power-state assumption.

Use the following sequence for the first schematic pass:

1. Select the exact device and package from Section 3.2 and Section 3.3.
2. Choose the correct power path: SF32LB520/3/5/7 for rechargeable battery-powered products, or 52B/D/E/G/J for externally regulated products.
3. Lock the power-system decisions in Section 5.2, including VBUS/VBAT/VCC or PVDD/VDDIOA/VDD_SIP, BUCK, internal LDO decoupling, RF/audio rails, and all low-power load switches.
4. Select the boot medium and populate PA13/PA17 bootstrap pull options to match the boot table in Section 5.6.1.
5. Route all boot-storage power switches to PA21, including large NOR Flash designs that must exit 4-byte mode after restart or Hibernate.
6. Reserve PA18/PA19, ground, and a valid power reference for DBG_UART/SWD access before the enclosure and production fixture are frozen.
7. Select the 48 MHz and 32.768 kHz crystals from Section 5.3.1 and keep their placement constraints visible during schematic review.
8. Assign wake pins, power-key behavior, charger events, and storage/sensor shutdown states before firmware low-power policy is finalized.

At the end of this gate, the schematic should be able to power up, boot from the selected medium, expose a recovery path, run clock calibration, and enter the intended low-power state without relying on optional product peripherals.

5.2. Power System¶

Power-system design defines the rails, load switches, charger path, OVP, internal LDO usage, wake behavior, and low-power states that make the minimum system reliable. Complete this section before PCB placement, because later display, storage, RF, audio, and sensor decisions depend on these rail assumptions.

5.2.1. Power Supply¶

Quick Summary

• Battery-powered devices use the SF32LB520/3/5/7 path with VBUS, VBAT, VCC, charging, and OVP decisions.
• Regular-powered devices use the 52B/D/E/G/J path with externally regulated PVDD, VDDIOA, VDD_SIP, and no internal charging path.
• BUCK inductor, internal LDO decoupling, RF/audio rails, and standby load switches must be fixed before PCB placement.

Design Goal

Create a stable, low-leakage power tree that supports the selected variant, avoids overloading internal LDO outputs, keeps RF and audio rails quiet, and allows unused loads and boot storage to be switched off in low-power modes.

5.2.1.1. Processor Power Supply Requirements¶

5.2.1.2. BUCK Inductor Selection¶

Both design groups use the same inductor specification.

5.2.1.3. Battery and Charging Control¶

5.2.1.4. Reducing Standby Power¶

5.2.1.5. Power Design Checklist¶

• Confirmed which power variant (battery-powered / regular-powered) matches the exact chip model
• BUCK inductor meets 4.7 uH ±20%, DCR ≤0.4 Ω, Isat ≥450 mA
• All internal LDO decoupling capacitors are placed per requirements
• LCD power is isolated and not fed directly from the internal LDO
• Audio and RF power rails are properly filtered
• Battery-powered variant: charging path and OVP device voltage ranges verified; regular-powered variant: VDD_SIP/VDDIOA supply configured correctly for the chip model

Common Mistakes - Power

• Powering the LCD directly from an internal LDO instead of an external LDO.
• Mixing battery-powered and regular-powered supply assumptions in the same schematic.
• Leaving VDD_SIP powered during Hibernate on variants where storage leakage is a risk.
• Choosing a charger or OVP device without verifying the worst-case VBUS current and voltage range.

Bring-Up Checks - Power

• Measure VCC/PVDD, BUCK output, RF/audio rails, and storage supply before firmware enables peripherals.
• Confirm charger attach, trickle charge, constant-current charge, and recharge behavior on battery-powered designs.
• Measure standby and Hibernate current with display, sensors, storage, and motor load switches off.

5.2.2. Operating Modes and Wake Sources¶

Quick Summary

• Active and Sleep retain fast interrupt response; DeepSleep and Standby trade wake time for lower current.
• Hibernate is the lowest-power state, but SRAM is not retained and some external supplies must be shut down.
• Wake-capable GPIO selection affects buttons, touch interrupt, charger events, and sensor wake behavior.

Design Goal

Select wake sources and external power-switch defaults so the product can enter the intended low-power state without leakage paths or missing wake events.

The whole family supports 15 wake-capable interrupt sources in Standby and Hibernate modes:

Operating-Mode Checklist

• Required wake pins are assigned before pin-mux is frozen.
• Pull states on wake pins are compatible with Standby and Hibernate.
• External storage and sensor supplies do not leak through I/O pins in Hibernate.
• Firmware and hardware teams agree which state is used for shipping, shelf, and normal standby modes.

5.3. Clock Generation¶

5.3.1. Crystal Selection¶

Quick Summary

• Use a 48 MHz main crystal and a 32.768 kHz RTC crystal.
• Favor low CL and low ESR parts from the AVL to reduce startup and static current.
• Keep crystal traces short, shielded, and away from heat, RF, charger, PMU, and DC/DC noise.

Design Goal

Provide stable, low-jitter clock sources while minimizing oscillator current, frequency drift, RF interference, and bring-up risk.

The chip requires two external clock sources: a 48 MHz main crystal and a 32.768 kHz RTC crystal. Requirements are identical for both variants.

Recommended crystals:

For the complete, continuously maintained qualification data, refer to the SiFli Approved Vendor List.

Common Mistakes - Clock

• Selecting a crystal only by frequency and package, without checking CL, ESR, tolerance, and temperature range.
• Placing the crystal near PA, charger, PMU, RF matching, or other heat/noise sources.
• Leaving copper or high-speed routing under the crystal keep-out region.
• Making 32 kHz traces long and parallel without spacing or ground shielding.

Clock Checklist

• 48 MHz and 32.768 kHz crystals match AVL/datasheet requirements.
• Crystal load capacitance and ESR are verified against the oscillator limits.
• Keep-out, trace length, trace width, spacing, and ground shielding are checked in PCB review.
• Bring-up plan includes measuring 48 MHz, 32 kHz, and Bluetooth frequency calibration behavior.

Continue to RF & User Interfaces.