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SF32LB52x Hardware Design Guide — PCB Layout Checklist

Part of the SF32LB52x Hardware Design Guide

This page covers Section 6.15, the item-by-item PCB layout checklist. Return to PCB Layout Guidelines.

6.15. PCB Layout Checklist

Unlike the schematic checklist, these layout rules don't vary by power variant, so there is no Applies To column — every check point applies to all SF32LB52x variants.

6.15.1. Package

Table 6.15-1: Package Checklist
No. Check Point Category
1 Footprint matches the package SPEC Required

6.15.2. Power Supply Routing

Table 6.15-2: Power Supply Routing Checklist
No. Check Point Category
1 VBUS supply trace ≥16 mil Required
2 VBAT supply trace ≥16 mil Required
3 VCC supply trace ≥12 mil Required
4 LDO2_OUT supply trace ≥10 mil Required
5 LDO3_OUT supply trace ≥8 mil Required
6 PMU_BUCK_VSW and PMU_BUCK_VOUT traces ≥10 mil Required
7 AVDD_BRF supply trace ≥8 mil Required
8 AVDD33_AUD supply trace ≥8 mil Required

6.15.3. Power Supply Capacitor and Inductor Placement

Table 6.15-3: Power Supply Capacitor and Inductor Placement Checklist
No. Check Point Category
1 VBUS capacitor placed close to the pin Required
2 VBAT capacitor placed close to the pin Optional
3 VCC capacitor placed close to the pin Required
4 LDO2_OUT capacitor placed close to the pin Optional
5 LDO3_OUT capacitor placed close to the pin Optional
6 VSYS capacitor placed close to the pin Required
7 BUCK inductor placed close to the chip Optional
8 BUCK decoupling capacitor placed as close as possible to the chip pin Required
9 VDD_HPSYS capacitor placed close to the pin Required
10 VDD_LPSYS capacitor placed close to the pin Required
11 VDD_RET capacitor placed close to the pin Required
12 VDD_RTC capacitor placed close to the pin Required
13 AVDD_BRF capacitor placed close to the pin Required
14 AVDD33_AUD capacitor placed close to the pin Required

6.15.4. Clock

Table 6.15-4: Clock Checklist
No. Check Point Category
1 Crystal placed close to the chip Required
2 GND shielding applied around the crystal Required
3 Copper keep-out applied under the crystal (4-layer PTH board: top layer; 6-layer HDI board: top layer and layer 2) Required
4 Ground-fill clearance along the crystal traces is greater than 1.5x the trace width Required
5 32 kHz crystal's parallel trace pair spacing is greater than 2x the trace spacing Required

6.15.5. Buttons

Table 6.15-5: Buttons Checklist
No. Check Point Category
1 Button's ESD protection device placed close to the button Required

6.15.6. RF

Table 6.15-6: RF Checklist
No. Check Point Category
1 RF trace meets the single-ended 50 Ω characteristic-impedance requirement Required
2 RF trace width ≥10 mil Required
3 At least 60 mil of ground on each side of the RF trace, with sufficient stitching vias to the main ground Required
4 Reserved Pi-type antenna matching network placed close to the chip side Required
5 Continuous GND plane beneath the RF signal Required
6 No high-speed digital signal traces cross beneath the RF signal Required
7 No high-di/dt power traces cross beneath the RF signal Required

6.15.7. Audio

Table 6.15-7: Audio Checklist
No. Check Point Category
1 ADCP is properly ground-guarded Required
2 DACP/DACN follow differential routing with ground guarding Required
3 DACP/DACN traces are short enough that parasitic capacitance stays below 10 pF Required
4 AVDD_BRF/AVDD33_AUD power routing is ground-guarded and kept away from high-current, strongly interfering signals Required

6.15.8. ADC

Table 6.15-8: ADC Checklist
No. Check Point Category
1 No high-speed signal runs parallel to the GPADC signal without ground guarding Required

6.15.9. Test Points

Table 6.15-9: Test Points Checklist
No. Check Point Category
1 Test-point locations are suitable for probing or fixture soldering Required
2 Program-download test points (VBAT, GND, PA18/DBG_UART_RXD, PA19/DBG_UART_TXD, LDO2_OUT, PA0, PA1, PA34, etc.) meet the size and location requirements of the test fixture Required

6.15.10. Ground

Table 6.15-10: Ground Checklist
No. Check Point Category
1 Layers adjacent to the main chip are a complete main-ground plane, with sufficient grounding vias Required
2 Exposed pad (EPAD) is connected to the main ground through vias Required
3 Area under the chip has enough grounding vias connected to the main ground plane Required
4 A ring of grounding vias runs around the board edge Required